Edge Effects on Gate Tunneling Current in HEMTs

We elucidate five considerations for accurate estimation of electron tunneling from the gate edges of high-electron mobility transistors (HEMTs). These considerations are listed as follows: 1) edge roughness; 2) net charge at the AlGaN/passivation interface; 3) dielectric constant of the medium above the HEMT surface; 4) nontriangular potential barrier; and 5) negligible angular tunneling from the gate edge. Using these considerations, we calculate the reverse gate current I_G of AlGaN/GaN HEMTs based on thermionic trap-assisted tunneling (TTT) and direct tunneling (DT) mechanisms. These calculations establish that the observed rise in I_G for a gate voltage beyond the threshold is due to tunneling from the gate edges. The calculations also show that the TTT mechanism can predict the measured I_G of AlGaN/GaN HEMTs over a wide range of gate voltages and temperatures and point to the possibility of a rapid rise in I_G at high gate voltages due to the DT mechanism.     

A novel model of the gate current in heterojunction FETs

The authors present a model of the gate current in heterojunction FETs that takes into account two-dimensional electron gas effects at the heterojunction interface. The gate current results from tunnel and thermionic contributions. This model takes into account a number of technological parameters such as heterojunction barrier height, threshold voltage, gate length, and temperature. It has been tested against experimental measurements of gate current in AlGaAs/GaAs MISFETs at various temperatures. The agreement has been found quite satisfactory in a large range of temperatures     

Dual work function metal gate CMOS transistors by Ni-Tiinterdiffusion

In this letter, we present dual work function metal gate complementary metal-oxide semiconductor (CMOS) transistors with thin SiO ₂ gate dielectric fabricated through the interdiffusion of nickel and titanium. The threshold voltage of the n-MOS devices is determined solely by Ti, while the threshold voltage of the p-MOS devices is determined by the Ni-rich alloy of Ti and Ni. The advantage of this new approach is that low threshold voltages for surface-channel n-MOS and p-MOS transistors can be achieved simultaneously. At the same time, the integrity of the gate dielectric is preserved since no metal has to be etched from the surface of the gate dielectric. With gate depletion eliminated, these transistors exhibit high inversion charge and drive current     

Temperature dependence of the anomalous leakage current inpolysilicon-on-insulator MOSFET's

A new analytical model is presented for the temperature and bias dependence of the anomalous leakage current based on thermionic field emission via grain boundary traps in the gate-drain overlap region in polysilicon-on-insulator MOSFET's. The existing model based on pure field emission (tunneling) via grain boundary traps does not include a temperature dependence and therefore cannot explain the observed strong temperature dependence of leakage at low gate voltages, as well as the weaker temperature dependence at high gate voltages, which the new analytical model presented in this paper can. Below 150 K, we believe that impact ionization due to the increasing carrier mean free path leads to the observed increase in the leakage current with decreasing temperature. Since the analytical model does not include impact ionization, it cannot model the leakage current at low temperatures     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Shielded silicon gate complementary MOS integrated circuit

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift inC-Vcurve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.     

Two-dimensional numerical analysis of the narrow gate effect in MOSFET

Lateral variation of the local threshold voltage causes non-linearity in the drain conductance-gate voltage characteristics, resulting in a nonunique external threshold voltage which varies with gate voltage. Using a 16-bit minicomputer, a two-dimensional (2-D) finite-difference program for narrow gate MOSFET (NAROMOS), and an accurate and efficient new finite-difference boundary equation at the oxide-semiconductor interface, computations are carried out for the external threshold voltage and a measurable electrical channel width as a function of the applied dc gate and substrate voltages. The depletion approximation is employed in order to compare the 2-D results with the 1-D analytical solution of the depletion model. Computed curves are presented for the lateral variations of the depletion layer thickness, surface potential, normal surface electric field, local as well as external threshold voltages, and electrical channel width as a function of the device structure, material parameters, and bias voltages. Based on the 2-D results and device physics, an analytical approximation of the threshold voltage versus the gate width, simple enough for CAD of VLSI, is derived whose parameters may be determined from either a 2-D computation or experimental measurements on one test device of a known gate width. The computed increase of the external threshold voltage with decreasing gate width compares well with published experimental data.     

An analysis of the temperature dependence of the gate current incomplementary heterojunction field-effect transistors

The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFETs) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods to reduce the gate current are discussed     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

Submicrometer MOSFET structure for minimizing hot-carrier generation

This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10^-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO2energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.     

Carbon-nanotube-based triode-field-emission displays using gatedemitter structure

We fabricated a carbon-nanotube-based triode-field-emission display with a gated emitter structure made up of a gate layer, a thin insulating layer, and a carbon nanotube layer. A low threshold voltage of 20 V and a total anode current of 0.5 mA at 80 V were observed for 30×30 pixel panels. We also demonstrated highly efficient and homogeneous emission from all pixels at voltages lower than 100 V. Based on simulation of electric fields in gate holes, further improvement of the emission properties is expected by optimizing its structural parameters, such as the gate-hole diameter     

A study of hot carrier degradation in NMOSEET's by gate capacitanceand charge pumping current

Hot carrier degradation in n-channel MOSFET's is studied using gate capacitance and charge pumping current for three gate stress voltages: V_g~V_b, V_d/2, V_d. The application of these two sensitive techniques reveals new information on the types of trap charges and the modes of degradation. At low V_g stress near threshold voltage, the fixed charge is attributed to holes. For high V_g stress, the fixed charge is predominantly electrons. Data for mid V_g stress suggest little net fixed charge trapping. Interface traps are observed for all stress conditions and are demonstrated from differential gate capacitance spectra to exhibit both donor and acceptor trap behavior. Mid V_g stress is shown to result in the highest density of interface traps. These traps can be annealed to a large extent for temperatures up to 300°C. A post-stress generation of interface traps is observed at low V_g stress, in agreement with recent observation. Further, a linear relation is found to exist between the change in overlap gate capacitance and the increase in peak charge pumping current, and suggests spatial uniformity in the degradation of the interface     

Emitter injection and collector current ideality in abrupt heterojunction AlInAs/GaInAs HBTs

We investigated the electron injection process for high-speed N-p-n AlInAs/GaInAs HBTs by measuring collector and base currents as a function of base-emitter voltage with collector-base voltage equal to zero (Gummel plots) at temperatures from 77 to 300 K. We compared the measured collector current with calculations based on electron injection from emitter to base by tunneling through the conduction band spike and thermionic emission over it, using a modified version of the thermionic-field emission theory developed by Crowell and Rideout. Good agreement was obtained between the experimental collector current ideality factor and tunneling-thermionic emission theory for all temperatures and currents. This is an improvement over drift-diffusion and thermionic emission models, which have been used for HBTs but which do not correctly describe the experimentally observed temperature and current dependence of the ideality of the collector current. The tunneling-thermionic emission model explains the increase in collector current ideality factor that occurs as the transistor is biased at high collector current density (J_C 10⁵ A cm⁻²), which is the regime of operation in which f_T is maximized and a low ideality factor is most important. The model also explains the experimentally observed variation of h_FE with ln I_C. Thus the tunneling-thermionic emission model is a useful aid in the design of the epitaxial structure for high-frequency HBTs.     

Thermionic emission model of electron gate current in submicronNMOSFETs

A thermionic emission model based on a non-Maxwellian electron energy distribution function for the electron gate current in NMOSFET's is described. The model uses hydrodynamic equations to describe more correctly the electron transport and gate injection phenomena in submicron devices. A generalized analytical function is used to describe the high-energy tail of the electron energy distribution function. Coefficients of this generalized function are determined by comparing simulated gate currents with the experimental data. This model also includes the self-consistent calculation of the tunneling component of the gate current by using the WKB approximation, and by using a more accurate representation of the oxide barrier by including the image potential. Good agreement with gate currents over a wide range of bias conditions for three different technological sets of devices are demonstrated by using a single set of coefficients     

A novel fabrication process of a silicon field emitter array withthermal oxide as a gate insulator

We have successfully developed a fabrication process of a silicon field emitter array with a gate insulator formed by Si₃N₄ sidewall formation and subsequent thermal oxidation. This process overcomes some problems in the conventional fabrication, such as high etch rate, low breakdown field, and gate hole expansion arising from evaporation of gate oxide. Therefore, we could improve process stability and emission performance, and also reduce gate leakage current. The optimum process conditions were determined by process simulations using SUPREM-4. The turn-on voltage of the fabricated field emitters was approximately 38 V. An anode current of 0.1 μA (1 μA) per tip was measured for a 625-tip array at the gate bias of 80 V (100 V), and the gate current was less than 0.3% of the anode current at those emission levels     

Substrate bias and operating temperature effects on the performance of Schottky-barrier SOI nMOSFETs

The substrate bias and operating temperature effects on the performance of erbium-silicided Schottky-barrier SOI nMOSFETs have been studied. The temperature dependence of the threshold voltage, the current ratio of I_ON/I_MIN, and the subthreshold swing has been investigated. From temperature dependence of the drain current, it is confirmed that the carrier transport mechanism changes from thermionic emission and tunneling at low gate voltage to drift-diffusion at the high gate voltage. By applying substrate bias voltage, the I_ON/I_MIN ratio and subthreshold swing can be improved. By investigating the substrate bias dependence of I_ON/I_MIN ratio, subthreshold swing, and DIBL, the optimum substrate bias voltage is suggested.     

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.     

Highly uniform and low turn-on voltage Si field emitter arraysfabricated using chemical mechanical polishing

Turn-on voltage of about 30 V is observed in 1-μm gate-aperture Si field emitter arrays fabricated using oxidation sharpening and chemical mechanical polishing. Small emitter tip radius (~10 nm) was achieved from low temperature oxidation sharpening. The gate leakage current is observed to be less than 0.01% of emitter current over the range of measurement. Devices show excellent emission uniformity for different sized arrays. Current saturation was observed at high gate voltages because of low dopant concentration of the substrate. Below the saturation region, the current-voltage characteristics obey the Fowler-Nordheim field emission theory     

Current/voltage characteristic collapse in AlGaN/GaNheterostructure insulated gate field effect transistors at high drainbias

The authors describe the current/voltage characteristic collapse under a high drain bias in AlGaN/GaN heterostructure insulated gate field effect transistors (HIGFETs) grown on sapphire substrates. These devices exhibit a low resistance state and a high resistance state, before and after the application of a high drain voltage, respectively. At room temperature, the high resistance state persists for several seconds. The device can also be returned into the low resistance state by exposing it to optical radiation. Electron trapping in the gate insulator near the drain edge of the gate is a possible mechanism for this effect, which is similar to what has been observed in AlGaAs/GaAs HFETs at cryogenic temperatures     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.