Role of the amplifying gate in the turn-on process of involutestructure thyristors

The switching characteristics of involute thyristors with and without the amplifying gate structure are discussed. The effects of peak gate currents (10-100 A) on the anode current di/dt, switching delay, and energy loss in both types of devices are presented. The performance of the devices without the amplifying gate was far superior than that of the devices with the amplifying gate. A model is presented to explain this difference. Thyristors without the amplifying gate successfully switched anode currents on the order of 12.6 kA, at a di/dt of 100000 A/μs, from an anode voltage of 2 kV on a single-shot basis     

Decrease of gate oxide dielectric constant in tungsten polycidegate processes

The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi_x) deposited either by chemical vapor deposition (CVD) or sputtering. For WSi_x deposited by CVD, it is found that the effective thickness of gate oxide as determined by CV measurement increases in all cases if the annealing temperature is 900°C or higher. However, high-resolution transmission electron microscopy (TEM) measurement indicates that the physical thickness does not change after a 900°C anneal. In this case, the dielectric constant of the gate oxide decreases by 7%. As the annealing temperature increases to 1000°C, CV and TEM measurements give the same thickness and the decrease of the dielectric constant disappears. In contrast, for WSi_x film deposited by sputtering, annealing at 900°C has no effect on the gate oxide thickness as measured by CV and TEM     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

Temperature sensitivity of phase-matched second-harmonic generationin LiIO3

Measurements were made of the temperature dependence (between 23 and 65°C) of the phase-matching angle &thetas;_pm for type I frequency doubling of 1064-nm laser light in lithium iodate (LiIO₃). The measured value of d&thetas;_pm/dT is -14.7±1 μrad/°C, which corresponds to a thermal sensitivity β_T =0.24±0.02 cm^-1/°C for this process. Also calculated is a value of d&thetas;_pm/dT using experimentally determined thermooptic data available in the literature. The calculated value of d&thetas;_pm/dT is -31±18 μrad/°C using literature values of n and dn/dT for LiIO₃. The extreme sensitivity of the calculated value of d&thetas;_pm/dT to small errors in the thermooptic coefficients may be the reason for this discrepancy     

Silicon-carbide high-voltage (400 V) Schottky barrier diodes

The authors describe the fabrication and characteristics of the first high-voltage (400-V) silicon-carbide (6H-SiC) Schottky barrier diodes. Measurements of the forward I-V characteristics of these diodes demonstrate a low forward voltage drop of ~1.1 V at an on-state current density of 100 A/cm² for a temperature range of 25 to 200°C. The reverse I-V characteristics of these devices exhibit a sharp breakdown, with breakdown voltages exceeding 400 V at 25°C. In addition, these diodes are shown to have superior reverse recovery characteristics when compared with high-speed silicon P-i-N rectifiers     

Demonstration of compact solid-state opening and closing switchutilizing GTOs in series

A compact opening and closing solid-state switch was designed, constructed, and demonstrated. The switch repetitively switches over 4 MW of peak power and yet is only 0.45 m by 0.12 m by 0.32 m and has a mass of 13 kg. The switch uses commercially available gate turn-off thyristors (GTOs), arranged in series to enable the collected devices to switch a voltage five times the rating of an individual device. The system uses commercially available components exclusively, yet takes advantage of state-of-the-art components. These include multilayer ceramic capacitors which are arrayed to produce a snubber capacitor, and small high-voltage isolated power transformers that protect each of the seven GTO stages from breakdown damage via their power supplies. Each stage is controlled via a fiber-optic link, and turn-on and turn-off times are adjustable for each of the seven stages. System dV/ dt exceeded 1 kV/μs and system di/dt exceeded 200 A/μs, for both turn-on and turn-off. The system was only limited in the amount of power it could switch by thermal considerations. A much higher power could be switched if there were advanced cooling. The cooling devices were quite modest, in that this was only a demonstration of the principle     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

A model for the temperature-dependent saturated ID-VD characteristics of an a-Si:H thin-filmtransistor

A simplified analytical expression for the temperature dependent saturated I_D-V_D characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors, between -50°C and 90°C, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled by a single equation. The model is based on three functions obtained from the experimental data of I_D versus V_G, over a range of temperature. Theoretical results confirm the simple form of the model in terms of the device geometry. As the temperature increased, the saturated drain current increased and, at a fixed gate voltage the device saturated at increasingly larger drain voltages while the threshold voltage decreased. Good agreement between the measured data and the model was obtained up to 363 K. Also observed at temperatures larger than 363 K was a decrease in I_D and more severe gate voltage hysteresis characteristics     

Temperature dependence of common-emitter I-V andcollector breakdown voltage characteristics in AlGaAs/GaAs andAlInAs/GaInAs HBT's grown by MBE

Temperature-dependent measurements from 25 to 125°C have been made of the DC I-V characteristics of HBTs with GaAs and In_0.53Ga_0.47As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV_CEO>10 V at 25°C, which increases with temperature. In striking contrast, the In_0.53Ga_0.47As HBTs have very high output conductance and low BV_CEO~2.5 V at 25°C, which actually decreases with temperature. This different behavior is explained by the >10⁴ higher collector leakage current, I_CO, in In_0.53Ga_0.47As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I-V characteristics     

AC/DC characterization of NMOS and PMOS hot-carrier-induceddegradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I_dsat shifts are compared following DC stress. The results of the I _dsat shifts are found to be the same. The AC I_dsat measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast (<20 ns). AC versus DC stressing was also examined. In PMOS devices, pulsed drain stress was found to be generally quasi-static, while pulsed gate stress produced enhanced device degradation under certain bias conditions. In NMOS transistors AC drain stress was found to be quasi-static in strong device saturation, while AC gate stress resulted in significantly enhanced degradation. In weak device saturation, both gate and drain pulsing resulted in early catastrophic device failure     

High-temperature Schottky diodes with thin-film diamond base

High-temperature (500-580°C) current-voltage (I-V ) characteristics of gold contacts to boron-doped homoepitaxial diamond films prepared using a plasma-enhanced chemical vapor deposition (CVD) method are described. Schottky diodes were formed using gold contacts to chemically cleaned boron-doped homoepitaxial diamond films. These devices incorporate ohmic contacts formed by annealing Au(70 nm)/Ti(10 nm) layers in air at 580°C. The experiments with homoepitaxial diamond films show that the leakage current density increases with the contact area. This implies that a nonuniform current distribution exists across the diode, presumably due to crystallographic defects in the diamond film. As a result, Au contacts with an area >1 mm² are essentially ohmic and can be used to form back contacts to Schottky diodes. Schottky diodes fabricated in this matter also show rectifying I-V characteristics in the 25-580°C temperature range     

High-energy pulse-switching characteristics of thyristors

Experiments were conducted to study the high energy, high di/dt pulse-switching characteristics of silicon controlled rectifiers (SCRs) with and without the amplifying gate. High di/dt, high-energy single-shot experiments were first done. Devices without the amplifying gate performed much better than the devices with the amplifying gate. A physical model is presented to describe the role of the amplifying gate in the turn-on process, thereby explaining the differences in the switching characteristics. The turn-on area for the failure of the devices was theoretically estimated and correlated with observations. This allowed calculation of the current density required for failure. Since the failure of these devices under high di/dt conditions was thermal in nature, a simulation using a finite-element method was performed to estimate the temperature rise in the devices. The results from this simulation showed that the temperature rise was significantly higher in the devices with the amplifying gate than in the devices without the amplifying gate. From these results, the safe operating frequencies for all the devices under high di/dt conditions was estimated. These estimates were confirmed by experimentally stressing the devices under high di/dt repetitive operation     

Study of the electronic trap distribution at the SiO2-Siinterface utilizing the low-frequency noise measurement

A correlation of the trap distribution at the silicon-oxide interface with the low-frequency noise measurement in MOS devices at temperatures ranging from 77 to 300 K is presented. Several devices with differently prepared gate oxides were used to study the process-induced trap distribution. Several peaks varying from sample to sample are found in a frequency index of noise spectrum versus temperature plot and are correlated with the discrete trap distribution across the bandgap of silicon. This method provides more information on traps as it circumvents the complexity of superimposing different traps which was encountered in the capacitance-voltage (C-V) method. Results, either compatible with others' work or consistent with data based on other measurements, show that the electronic trapping behavior in MOS structures is governed by two intrinsic traps located at 0.12 and 0.3 eV (both measured from the conduction band) for all kinds of oxides. In addition, dry oxidation was found to introduce an additional trap at an energy level of 0.23 eV, and annealing the gate oxide in ammonia at a high temperature (>1000°C) results in an enhancement of the trap density of 0.43 eV below the conduction band edge of silicon, which was also observed in a quasi-static C-V measurement     

Direct evidence of gate oxide thickness increase in tungstenpolycide processes

The increase of the effective gate oxide thickness for W-polycide processes is studied. The samples with as-deposited and annealed W polycide were analyzed by secondary ion mass spectrometry, transmission electron microscopy (TEM), and high-frequency CV measurements. The TEM cross section shows that the gate oxide thicknesses are ~244 and ~285 Å for as-deposited and 1000°C annealed samples, respectively. The TEM results agree with those from CV measurements. The TEM analyses provide direct physical evidence of an additional oxide thickness (~41 Å) during the W-polycide annealing     

Nonlinear GaAs MESFET modeling using pulsed gate measurements

The effects of traps in GaAs MESFETs are studied using a pulsed gate measurement system. The devices are pulsed into the active region for a short period (typically 1 μs) and are held in the cutoff region for the rest of a 1-ms period. While the devices are on, the drain current is sampled and a series of pulsed gate I-V curves are obtained. The drain current obtained under the pulsed gate conditions for a given V_GS and V_DS gives a better representation of the instantaneous current for a corresponding V_gs and V_ds in the microwave cycle because of the effects of traps. The static and pulsed gate curves were used in a nonlinear time-domain model to predict harmonic current. The results showed that analysis using pulsed gate curves yielded better predictions of harmonic distortion than analysis based on conventional state I-V curves under large-signal conditions     

A narrow bandpass microstrip filter for high-speed fiber opticsystems

Transmission systems employing passively retimed regenerators require a bandpass timing filter to extract the timing wave from the data stream. Typically, filters with Q exceeding 100 are necessary in long-haul fiber-optic systems. The fabrication of a microstrip filter with a loaded Q of over 500 and an insertion loss of 8 dB, is reported. The midband return loss in 4.8 dB. The filter is fabricated on a 1-in×1-in×1-in Ba₂Ti₉ O₂₀ substrate. This material has a dielectric constant of about 39 and can be formulated with temperature coefficients of resonant frequency from -2 to +6 p.p.m./°C. The fabricated device has a temperature coefficient of +2 p.p.m./°C. This combination of material properties facilitates high Q and small filter size and has the potential to compensate for temperature-induced electronic phase shifts between signal and clock recovery paths to the bit-decision circuit     

Low-temperature DC characteristics of pseudomorphic Ga0.18In0.82P/InP/Ga0.47In0.53As HEMT

A high-gap strained GaInP material chosen to increase Schottky barrier height on InP is discussed. This material has been used for the first time in high electron mobility transistor (HEMT) fabrication on InP. For these devices the best g_m of a 1.3-μm gate HEMT is 300 mS/mm. Transistors of 3-μm gate length are studied at low temperature (100 to 293 K). Their DC electrical characteristics improve upon cooling. The best improvement is measured at the lowest temperature (+54% for g_m at 105 K). The structure is stable and does not present any g_m or I_ds collapse at low temperature, unlike AlGaAs/GaAs heterostructures     

Collector-assisted operation of micromachined field-emitter triodes

The field at the tip of a field emitter triode can be expressed by E=βV_g+_γV _c, where V_g and V_c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, _γV_c<<βV _g. The-device is operated in the gate-induced field emission mode and the corresponding I-V_c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I-V_c and transconductance g_m-V_g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly     

AlInAs-GaInAs HEMTs utilizing low-temperature AlInAs buffers grownby MBE

Low-temperature AlInAs buffer layers incorporated in AlInAs-GaInAs HEMT epitaxial layers grown by MBE are discussed. A growth temperature of 150°C followed by a short anneal is shown to eliminate kinks in the device I-V characteristic and sidegating and to reduce the output conductance dramatically