A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.     

A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-/spl mu/m CMOS

This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54/spl deg//1.1/spl deg/ for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.     

A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.     

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.     

一种应用于IEEE 802.11 b/g/n无线局域网收发机的CMOS模拟基带电路

本文提出了一种应用于直接变频无线局域网收发机的模拟基带电路,该电路采用标准的0.13微米CMOS工艺实现,包括了采用有源RC方式实现的接收4阶椭圆低通滤波器、发射3阶切比雪夫低通滤波器、包含直流失调消除伺服环路的接收可变增益放大器及片上输出缓冲器。芯片面积共1.26平方毫米。接收基带链路增益可在-11dB至49dB间以2dB步长调节。相应地,基带接收输入等效噪声电压（IRN）在50 nV/sqrt(Hz) 至30.2 nV/ sqrt(Hz)间变化而带内输入三阶交调（IIP3）在21dBm至-41dBm间变化。接收及发射低通滤波器的转折频率可在5MHz、10MHz及20MHz之间选择以符合包含802.11b/g/n的多种标准的要求。接收基带I、Q两路的增益可在-1.6dB至0.9dB之间以0.1dB的步长分别调节以实现发射IQ增益失调校正。通过采用基于相同积分器的椭圆滤波器综合技术及作用于电容阵列的全局补偿技术,接收滤波器的功耗显著降低。工作于1.2V电源电压时,整个芯片的基带接收及发射链路分别消耗26.8mA及8mA电流。     

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-/spl mu/m CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8/spl deg/ rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm/sup 2/.     

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of-3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7×4.2 mm2.     

A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard

A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency control is implemented in a 0.18-/spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution The transceiver consumes 150 mW in receive mode and 380 mW in transmit mode while transmitting +15-dBm output power. The receiver achieves a sensitivity of better than -93.7dBm and -73.9dBm for 6 Mb/s and 54 Mb/s, respectively (even using hard-decision decoding). The transceiver achieves a 4-dB receive noise figure and a +23-dBm transmitter saturated output power. The transmitter also achieves a transmit error vector magnitude of -33 dB. The IC occupies a total die area of 11.7 mm/sup 2/ and is packaged in a 48-pin LPCC package. The chip passes better than /spl plusmn/2.5-kV ESD performance. Various integrated self-contained or system-level calibration capabilities allow for high performance and high yield.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

A highly integrated dual-band multimode wireless LAN transceiver

A fully integrated radio transceiver chip for the 2.4- and 5-GHz WLAN standards 802.11a/b/g is presented in a 0.25-/spl mu/m 40-GHz BiCMOS technology. The chip integrates the low-noise amplifiers, mixers, channel filters, programmable gain control, synthesizers with voltage-controlled oscillators and reference oscillator, transmitters, antialiasing filters, and voltage regulators. The key performances of the presented transceiver are a receive sensitivity of -85 dBm and -74 dBm for 11-Mb/s complementary code keying (CCK) and 54 Mb/s orthogonal frequency division multiplexing (OFDM) modes, respectively, and an error vector magnitude of -35 dB measured at the transmitter with an output power of -4 dBm at 54-Mb/s 802.11a mode. The transceiver exceeds all IEEE requirements for the 802.11a/b/g CCK and OFDM standards and supports a frequency range of 4.9 to 6 GHz for the future extensions of the 802.11a standard in different countries.     

A direct-conversion CMOS transceiver for the 802.11a/b/g WLAN standard utilizing a Cartesian feedback transmitter

A fully integrated dual-band transceiver is implemented in 0.18-/spl mu/m CMOS and is compliant with the IEEE 802.11a/b/g standards. The direct-conversion transceiver occupies 12 mm/sup 2/ in a QFN-40 package. A fractional-N synthesizer operates at twice the channel frequency, covering continuously bands from 4.9 to 5.9 GHz, as well as the 2.4-GHz band. The 5- and 2.4-GHz receivers achieve a sensitivity level below -73 dBm in the 54-Mb/s mode and below -93 dBm in the 6-Mb/s mode, while consuming 230 mW. A fast RSSI-channel power-detection system allows to power-down signal processing in the listen mode. The 5- and 2.4-GHz transmitters implement a wideband Cartesian feedback loop for enhanced EVM performances and improved spectrum masks compliance. The transmitters deliver -2-dBm average power with an EVM of 3% in the 54-Mb/s mode while consuming 300 mW.     

An auto-I/Q calibrated CMOS transceiver for 802.11g

The CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with an auto-I/Q calibration function for IEEE 802.11g. The transceiver supports I/Q gain and phase mismatch auto tuning mechanisms at both the transmitting and receiving ends, which are able to reduce the phase mismatch to within 1/spl deg/ and gain mismatch to 0.1dB. Implemented in a 0.25 /spl mu/m CMOS process with 2.7 V supply voltage, the transceiver delivers a 5.1 dB receiver cascade noise figure, 7 dBm transmit, and a 1 dB compression point.     

A novel link adaptation scheme to enhance performance of IEEE 802.11g wireless LAN

A novel link adaptation scheme using linear Auto Regressive （AR） model channel estimation algorithm to enhance the performance of auto rate selection mechanism in IEEE 802.11g is proposed. This scheme can overcome the low efficiency caused by time interval between the time when Received Signal Strength （RSS） is measured and the time when rate is selected. The best rate is selected based on data payload length, frame retry count and the estimated RSS, which is estimated from recorded RSSs. Simulation results show that the proposed scheme enhances mean throughput performance up to 7%, in saturation state, and up to 24% in finite load state compared with those non-estimation schemes, performance enhancements in average drop rate and average number of transmission attempts per data frame delivery also validate the effectiveness of the proposed schelne.     

A survey of QoS enhancements for IEEE 802.11 wireless LAN

Quality‐of‐service (QoS) is a key problem of today's IP networks. Many frameworks (IntServ, DiffServ, MPLS etc.) have been proposed to provide service differentiation in the Internet. At the same time, the Internet is becoming more and more heterogeneous due to the recent explosion of wireless networks. In wireless environments, bandwidth is scarce and channel conditions are time‐varying and sometimes highly lossy. Many previous research works show that what works well in a wired network cannot be directly applied in the wireless environment. Although IEEE 802.11 wireless LAN (WLAN) is the most widely used IEEE 802.11 wireless LAN (WLAN) standard today, it cannot provide QoS support for the increasing number of multimedia applications. Thus, a large number of 802.11 QoS enhancement schemes have been proposed, each one focusing on a particular mode. This paper summarizes all these schemes and presents a survey of current research activities. First, we analyze the QoS limitations of IEEE 802.11 wireless MAC layers. Then, different QoS enhancement techniques proposed for 802.11 WLAN are described and classified along with their advantages/drawbacks. Finally, the upcoming IEEE 802.11e QoS enhancement standard is introduced and studied in detail. Copyright © 2004 John Wiley & Sons, Ltd.     

A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs

This paper describes a radio-frequency receiver targeting spread-spectrum wireless local-area-network applications in the 2.4-GHz band. Based on a direct-conversion architecture, the receiver employs partial channel selection filtering, dc offset removal, and baseband amplification. Fabricated in a 0.6-μm CMOS technology, the receiver achieves a noise figure of 8.3 dB, IP₃ of -9 dBm, IP₂ of +22 dBm, and voltage gain of 34 dB while dissipating 80 mW from a 3-V supply     

A novel performance analysis model for an IEEE 802.11 wireless LAN

This letter presents a novel analytic model that accurately evaluates the performance of a single-hop IEEE 802.11 wireless LAN (WLAN). By using a closed queuing network, we model an IEEE 802.11 WLAN system that consists of a fixed number of stations and derive the saturated throughput of the IEEE 802.11 distributed coordination function (DCF). The ns-2 simulation results show that our new analysis model is very accurate in evaluating the performance of the IEEE 802.11 DCF.     

A low flicker noise direct conversion receiver for IEEE 802.11g wireless LAN using differential active inductor

In this paper, a low flicker-noise, 2.4 GHz direct onversion receiver (DCR) has been designed. A dynamic current injection (DCI) technique has been utilized in addition with a tuning inductor in the mixing stage. The tuning inductor has been replaced by a differential active inductor circuit, which gives the same inductance, with less chip size and high quality factor. The DCR has been designed in a TSMC 0.18 μm 1P6M CMOS process for wireless LAN 802.11g applications. The proposed DCR achieves 6.7 dB SSB-NF, 34 dB conversion gain, −13.5 dBm IIP3, and flicker noise (1/f) corner frequency of 30 kHz with 137.5 mW power consumption from 1.8 V supply voltage.     

A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications

A 2.4GHz CMOS monolithic transceiver front-end for IEEE 802.11b wireless LAN applications is presented.The receiver and transmitter are both of superheterodyne structure for good system performance.The front-end consists of five blocks:low noise amplifier,down-converter,up-converter, pre-amplifier,and LO buffer.Their input/output impedance are all on-chip matched to 50Ω except the down-converter which has open-drain outputs.The transceiver RF front-end has been implemented in a 0.18μm CMOS process.When the LNA and the down-converter are directly connected,the measured noise figure is 5.2dB,the measured available power gain 12.5dB,the input 1dB compression point -18dBm,and the third-order input intercept point -7dBm.The receiver front-end draws 13.6mA currents from the 1.8V power supply.When the up-converter and pre-amplifier are directly connected,the measured noise figure is 12.4dB,the power gain is 23.8dB,the output 1dB compression point is 15dBm,and the third-order output intercept point is 16dBm.The transmitter consumes 276mA current from the 1.8V power supply.