HDP介质淀积引起的等离子充电损伤机制研究

高密度等离子体化学气相淀积(HDP CVD),具有卓越的填孔能力和可靠的电学特性等诸多优点,因此它被广泛应用于超大规模集成电路制造工艺中.本文研究了金属层间介质(IMD)的HDP CVD过程对栅氧化膜的等离子充电损伤.研究表明在HDP淀积结束时的光电导效应使得IMD层(包括FSG和USG)在较短的时间内处于导电状态,较大电流由IMD层流经栅氧化膜,在栅氧化膜中产生缺陷,从而降低了栅氧化膜可靠性.通过对HDP CVD结束后反应腔内气体组分的调节,IMD层的光电导现象得到了一定程度的抑制,等离子充电损伤得到了改善.     

GaAs衬底上低温热分解生长扩散掩膜

一、引言GaAs器件和Si器件一样,也常常需要一种钝化膜来提高器件的可靠性,或是作为杂质选择扩散的掩膜。目前GaAs器件常用的介质膜有Si_3N_4膜、SiO_2膜、Al_2O_3膜和GaAs自身氧化膜(阳极氧化、等离子氧化等) 用正硅酸乙酯热分解生成SiO_2膜和PSG膜是硅平面工艺中常用的方法,这种方法工艺简单、安全、容易控制。但在GaAs衬底上如用Si器件的热分解工艺,当分解温度为700℃—800℃时,会使GaAs表面离解,造成缺陷,影响器件的电参数。为了防止GaAs衬底的分解,我们在尽可能低的温度下,预先在GaAs衬底上淀积一层薄膜,此膜可以     

采用有机源的金属层间膜的平坦化技术

一、前言随着器件的高集成化、高速化和高功能化，器件表面台阶越来越陡峭。特别是进入亚微米时代，由于微细化和高电流密度的要求，金属布线的纵横尺寸比明显增大。所以，在扩展光刻极限的同时，从提高产品成品率、可靠性上来说，平坦化技术是一项极为重要的技术课题。图1示出了具有代表性的金属层间平坦化技术动向及其存在的问题。以往，要求低温工艺的金属层间绝缘股平坦化技术一般是采用等离子氧化股[P（等离子）－SiO2膜或P－TEOS膜等]与涂敷绝缘膜（SOG膜等）相结合的叠层结构，并在此结构上采用返腐蚀工艺或等离子氧化膜和抗蚀…     

长波碲镉汞材料阳极氧化膜/ZnS界面的电学特性参数

通过碲镉汞阳极氧化膜和磁控溅射ZnS膜,结合HgCdTe器件工艺,成功制备了以阳极氧化膜和磁控溅射ZnS双层钝化膜为绝缘层的“长波弱P”型HgCdTe MIS器件.通过对器件的C-V特性实验分析,获得了长波HgCdTe材料的阳极氧化膜/ZnS界面电学特性参数.并通过获得的界面参数,计算了阳极氧化和ZnS的双层钝化膜的表面复合速度.并对MIS器件的变温C-V特性进行了实验和分析.     

国产CF4＋O2混合气体在Si3N4腐蚀中的应用

一、引言Si3N4膜的腐蚀是一个比较老的课题，早在70年代的发光二极管器件制造中就开始了等高于腐蚀Si3N4的应用。目前，在大规模集成电路制造工艺中，Si3N4膜通常作为局部氧化（LOCOS）掩模材料，因此如何刻蚀好Si3N4就显得比较重要。随着器件尺寸的不断缩小，为了消除或最大限度地抑制鸟嘴对有源区的侵入，要求Si3N4层下面的SiO2厚度越来越薄，以确保有源区面积，同时为防止刻蚀中等离子辐射对衬底Si的损伤，影响器件的电特性及成品率，要求在等离子刻蚀中Si3N4膜对SiO2有高的选择性、均匀性，以及解决颗粒沾污问题。刻蚀Si3N4的…     

浅谈等离子氧化技术

本文简述了等离子氧化技术,这是国外近年来研究的一种低温、干法氧化工艺。它对于硅和化合物半导体的氧化有着独特的优点,是一种很有希望的新工艺。本文重点介绍了这种技术的基本原理、产生氧等离子体的几种方法、氧化工艺、氧化膜特性及在器件中的应用。     

大功率半导体激光器腔面处理方法

介绍了采用非注入电流腔面和透明窗口减小腔面电流的方法。减小腔面非辐射复合的方法包括采用高真空下解理、镀膜防止腔面氧化;采用真空等离子洗或化学气体腐蚀清除腔面氧杂质沾污。论述了合适的腔面膜系组合和膜系组分有利于减小腔面膜层应力,改善散热能力。指出将抑制腔面电流、防止腔面氧化等方法组合,再加上合理的结构设计和热管理等综合应用,以及将半导体材料-镀膜膜层交界面处于光驻波波谷,可有效提高器件的灾变光学镜面损伤(COMD)阈值。     

反应离子刻蚀铝中nMOS 器件的等离子充电损伤

介绍在等离子工艺中的等离子充电损伤,并且利用相应的反应离子刻蚀(RIE)Al的工艺试验来研究在nMOSFET器件中的性能退化。通过分析天线比(AR)从100:1到10000:1的nMOSFET器件的栅隧穿漏电流,阈值Vt漂移,亚阈值特性来研究由Al刻蚀工艺导致的损伤。试验结果表明在阈值Vt漂移中没有发现与天线尺寸相关的损伤,而在栅隧穿漏电流和低源漏电场下亚阈值特性中发现了不同天线比的nMOS器件有相应的等离子充电损伤。在现有的理解上对在RIEAl中nMOS器件等离子充电损伤进行了讨论,并且基于这次试验结果对减小等离子损伤提出了一些建议。     

表面二次阳极氧化对HgCdTe光导器件性能的影响

采用微波光电导衰退法(μ-PCD)测试了二次阳极氧化膜和传统氧化膜钝化的中波n型HgCdTe芯片的少子寿命.利用俄歇电子能谱(AES)研究了传统方法与新方法生成的氧化膜的组分变化.结果表明二次阳极氧化能显著提高少数载流子寿命,采用此工艺制作的光导器件的信号、响应率、D·优于常规方法制作的器件.     

InSb阳极氧化膜界面特性研究

用阳极氧化的方法在InSb衬底上生长氧化膜,并在阳极氧化膜上镀Cr/Au电极以制备MOS器件,通过分析77 K时MOS器件C-V特性,得出InSb-阳极氧化膜界面的掺杂浓度、界面态密度,氧化层中的固定电荷密度可动电荷密度等重要参数,分析其界面特性和制备工艺的关系,为InSb表面的钝化工艺提供参考.     

Influence of growth conditions of oxide on electrical properties of AlGaN/GaN metal–insulator–semiconductor transistors

AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors(MIS-HEMTs) on a silicon substrate were fabricated with silicon oxide as a gate dielectric by sputtering deposition and electron-beam(EB) evaporation. It was found that the oxide deposition method and conditions have great influences on the electrical properties of HEMTs. The low sputtering temperature or oxygen introduction at higher temperature results in a positive equivalent charge density at the oxide/AlGaN interface(Nequ), which induces a negative shift of threshold voltage and an increase in both sheet electron density(ns) and drain current density(ID). Contrarily, EB deposition makes a negative Nequ, resulting in reduced ns and ID. Besides, the maximum transconductance(gm-max) decreases and the off-state gate current density(I_G-off) increases for oxides at lower sputtering temperature compared with that at higher temperature, possibly due to a more serious sputter-induced damage and much larger Nequ at lower sputtering temperature. At high sputtering temperature, I_G-off decreases by two orders of magnitude compared to that without oxygen, which indicates that oxygen introduction and partial pressure depression of argon decreases the sputter-induced damage significantly. I_G-off for EB-evaporated samples is lower by orders of magnitude than that of sputtered ones, possibly attributed to the lower damage of EB evaporation to the barrier layer surface.     

A comparison of CVD stacked gate oxide and thermal gate oxide for0.5-μm transistors subjected to process-induced damage

Process-induced damage of gate oxide or of the Si-SiO₂ interface may result in device degradation problems such as threshold voltage scatter. The problem is especially pronounced for submicrometer technology. In addition to offering a low area defect density, a thermal/CVD stacked gate oxide decreases process-induced device degradation dramatically as compared with thermal gate oxide. Hot carrier injection stressing and Fowler-Nordheim stressing were performed to investigate the robustness of CVD stacked gate oxide. The effect of densification of the stacked gate oxide on electrical channel length was studied with supporting SEM analysis. An optimal value for the thickness ratio of CVD to thermal oxide for stacked gate dielectric was observed for minimum defect density of 150-Å gate dielectric     

Back-gated buried oxide MOSFETs in a high-voltage bipolartechnology for bonded oxide/SOI interface characterization

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2×10¹²/cm² at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4×10¹⁰/cm² in the buried oxide     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

A high-quality stacked thermal/LPCVD gate oxide technology for ULSI

By stacking thermal and high-quality LPCVD (low-pressure chemical vapor deposition) SiO₂ films, gate oxides with very low defect densities are demonstrated. Whereas previous reports suggested that a thick layer of LPCVD oxide can improve the stacked gate oxide defect density, it is demonstrated that even 25 Å of LPCVD oxide is sufficient to dramatically reduce the defect density compared to thermal oxide films. The projected scaling limit for this technology is estimated to be as low as 70 Å for the total stack thickness. An optimized thermal/LPCVD oxide technology is very promising as the gate dielectric for sub-half-micrometer CMOS technology     

The effect of native oxide on thin gate oxide integrity

We have studied the effect of native oxide on thin gate oxide integrity. Much improved leakage current of gate oxide can be obtained by in situ desorbing the native oxide using HF-vapor treated and H₂ baked processes. Furthermore, an extremely sharp interface between oxide and Si is obtained, and good oxide reliability is achieved even under a high current density stress of 11 A/cm² and a large charge injection of 7.9×10⁴ C/cm². The presence of native oxide will increase the interface roughness, gate oxide leakage current and stress-induced hole traps     

GaAs MOSFET using InAlP native oxide as gate dielectric

GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39/spl times/10/sup -7/ mA//spl mu/m/sup 2/ at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 /spl mu/m. Devices with 2-/spl mu/m-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage.     

Effects of radiation and charge trapping on the reliability of high-κ gate dielectrics

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO₂ are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to 15 to 20 times larger than thermal SiO₂ of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high-κ gate dielectrics in a space environment.     

Low-Frequency Noise Assessment of Silicon Passivated Ge pMOSFETs With TiN/TaN/ HfO2 Gate Stack

The low-frequency noise of pMOSFETs fabricated in epitaxial germanium-on-silicon substrates is studied. The gate stack consists of a TiN/TaN metal gate on top of a 1.3-nm equivalent oxide thickness HfO₂/SiO₂ gate dielectric bilayer. The latter is grown by chemical oxidation of a thin epitaxial silicon film deposited to passivate the germanium surface. It is shown that the spectrum is of the 1/f^gamma type, which obeys number fluctuations for intermediate gate voltage overdrives. A correlation between the low-field mobility and the oxide trap density derived from the 1/f noise magnitude and the interface trap density obtained from charge pumping is reported and explained by considering remote Coulomb scattering     

Anodic oxide film as gate insulator for InP MOSFETs

An anodic oxide film of InP, which had an interface state density of ? 1011 cm?2 eV?1 near midgap and worked well as the gate insulator for InP MOSFETs, was obtained by optimising its preparation conditions. The excellence of the anodic oxide as a gate insulator was confirmed by a high electron effective mobility (1500 cm2/Vs) in the accumulation-mode InP MOSFETs.