Reliability of power GaAs field-effect transistors

The first report on a comprehensive study of the reliability of power GaAs FET's with aluminum gates and silicon-nitride passivation is presented. A total of 265 standard 6-mm-wide devices has been aged under dc-bias conditions with and without RF drive at channel temperatures of 250, 210, and 175°C. One-million device-hours have been accumulated with no catastrophic failure. A very conservative estimate predicts that the failure rate for burnout at a maximum channel temperature in normal operation of 110°C would be below 100 FIT's. Degradation in the electrical parameters has been very slow even at 250°C channel temperature. It is estimated that the failure rate for gradual degradation at 110°C would be well below 100 FIT's and most likely lower than 10 FIT's. No deterioration in the properties of gates and ohmic contacts have been observed. Diagnostic characterization has revealed that gradual degradation in the sample devices is caused by deterioration in the channel material. There has been no noticeable difference in gradual degradation between devices aged with and without RF drive at the same channel temperature for more than 3000 h. The present study has already demonstrated that the power GaAs FET's used as the samples are very reliable.     

Extraction and modeling of self-heating and mutual thermal coupling impedance of bipolar transistors

A measurement system comprised of an ultra-low-distortion function generator, lock-in amplifier, and semiconductor parameter analyzer is used for sensitive extraction of the small-signal thermal impedance network of bipolar devices and circuits. The extraction procedure is demonstrated through measurements on several silicon-on-glass NPN test structures. Behavioral modeling of the mutual thermal coupling obtained by fitting a multipole rational complex function to measured data is presented.     

A physics-based dynamic thermal impedance model for verticalbipolar transistors on SOI substrates

A physics-based compact model for the thermal impedance of vertical bipolar transistors, fabricated with full dielectric isolation, is presented. The model compares favorably to both three dimensional (3-D) ANSYS(R) transient simulations and measurements. Using the software package Thermal Impedance Pre-Processor (TIPP), a multiple-pole circuit can be fitted to the thermal impedance model. The thermal equivalent circuit is used in conjunction with a modified version of SPICE to give efficient electrothermal simulations in the dc and transient regimes     

Transconductance degradation in VVMOS power transistors due to thermal and field effects

A relatively simple transconductance equation for the VVMOS power transistor is presented in this paper. Temperature and gate voltage dependent surface mobility as well as temperature dependent surface saturation velocity are shown to be responsible for transconductance degradfation. Theoretical results are in very good agreement with experimental measurements over a wide range of gate voltages.     

Study of thermal effects and self-heating phenomena in planar power SOI MOS transistors

Heat removal problems, thermal effects, and self-heating phenomena occurring during operation of planar power SOI MOS transistors are considered. Using device-technological simulating methods, the transistor characteristics and safe operation range were studied. It was shown that limitations of the safe operation range are mostly associated with structure self-heating rather than with the parasitic bipolar transistor.     

Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

The total safe operating area of both lateral and vertical integrated DMOS power transistors is evaluated. The electrical, hot carrier and thermal safe operating area of both devices types is investigated, and a comparison is made. It is found that the vertical DMOS exhibits a superior hot carrier and electrical safe operating area, mainly being due to the absence of a field oxide dot in the device drift region. The thermal safe operating area of LDMOS and VDMOS is identical.     

Correlation impedance in transistors at high injection

It is shown that the correlation impedance R_cor of a p⁺-n-p transistor at high injection and low frequencies is given as $\text{R}{}_{\mathrm{<mtext>cor</mtext>}}\text{= 2(}\text{μ}{}_{\mathrm{<mtext>p</mtext>}}\text{μ}{}_{\mathrm{n}}\text{)(}\text{k}\text{T}\text{q}\text{I}{}_{\mathrm{<mtext>Ep</mtext>}}\text{)}$, which is small for silicon transistors. For n⁺-p-n transistors under the same conditions $\text{R}{}_{\mathrm{<mtext>cor</mtext>}}\text{= 2(}\text{μ}{}_{\mathrm{n}}\text{μ}{}_{\mathrm{p}}\text{)(}\text{k}\text{T}\text{q}\text{I}{}_{\mathrm{<mtext>EP</mtext>}}\text{)}$, which is large for silicon transistors. This strong asymmetry between p⁺-n-p and n⁺-p-n silicon transistors should be measurable.     

Some new aspects of thermal instability of the current distribution in power transistors

An important characteristic of second breakdown in p-n junctions is the current constriction to a small region. This may be caused by a thermal feedback mechanism, as discussed by Scarlett and Shockley, and by Bergmann and Gerstner. A brief review of this theory is given, illustrated by experimental results of a simple model arrangement consisting of three thermally coupled transistors. The essential parameters influencing the thermal stability of the current distribution are device geometry, power density, and temperature dependence of current. It is widely known that second breakdown occurs at high voltages at a much lower power level than at low voltages. To allow a more detailed discussion of this effect in view of thermal stability, we determined experimentally the temperature coefficient of transistor current for various Si planar transistors as a function of current, voltage, and junction temperature. The experimental procedure is described and the results are discussed. The experimental values of the temperature coefficient range from 0.08 to 0.01 1/°C. The values for high currents are much lower than predicted by the theory of Ebers and Moll. It thus can easily be understood why, in the case of high current, and low voltage, the thermal stability of the current distribution is much better than in the case of low current and high voltage.     

Novel approach of twin-side thermal interfacing of integrated power modules for reduced thermal impedance

A novel approach of twin-side thermal interfaces of integrated power modules (IPM) is presented. This approach applies and improves commercially off-the-shelf products of IPM without significantly changing the original packaging design and manufacture's fabrication process. This approach can reduce the equivalent thermal impedance of the power module by about 20 %. It, in turn, reduces the p-n junction temperature rise of the power devices inside by 20 % at an equivalent load, thus being able to increase ambient operating temperatures, which is desirable for automotive applications. In addition, the weight and volume associated with conventional cooling mechanism can be reduced.     

Hot-spot thermal resistance in transistors

By the application of an infrared radiometer as the sensor, hot-spot formation is detected and a hot-spot thermal resistance is calculated. Hot-spot formation for both forward- and reverse-biased second breakdown is analyzed. Pulsed dc techniques are used in the investigation, allowing a wide range of possible operating biases to be applied.     

Application of the TLM method to transient thermal simulation ofmicrowave power transistors

The transmission line matrix (TLM) explicit method of numerical simulation has been used to model the transient thermal properties of various microwave heterojunction bipolar transistor (HBT's) power structures, used in a pulsed mode. Control of the time step during the simulation is of paramount importance and the paper outlines some of the problems encountered using time step control methods currently published and describes an improved algorithm. This improved time step control method has been implemented in a general purpose 3D TLM transient thermal simulator. Some simulation results are described for a variety HBT transistor structures with very different thermal time constants     

Reliability of soldered joints in CSPs of various designs andmounting conditions

The chip size package (CSP) is being used in various portable electronic products recently. Further evaluation of the reliability of its soldered joints is required all the more now because those soldered joints are invisible. This study focused on the thermal fatigue life of soldered joints in the CSP. CSPs were mounted on printed circuit boards (PCBs) in various configurations and mounting conditions, and underwent thermal cycle testing. Then, the fatigue lives of their soldered joints were compared. As a result, the following two facts became apparent. First, reflowing at a 210°C peak tends to result in failures that may be derived from poor wetting between solder and pad, in cases where the CSP is mounted on a nickel and gold plated pad. And second, the size of the soldered joint has a great influence on its fatigue life. The larger the soldered joints that we made, the longer fatigue life they indicated. A finite element method (FEM) analysis of those mounted structures was also executed. Viscoplastic (creep and plastic) property of solder was evaluated to compute equivalent inelastic strain occurring in the joints. A parameter in the Coffin-Manson equation is obtained from the computed inelastic strain amplitudes and the experimented actual fatigue lives. This result will enable estimation of the fatigue life of soldered joints of the CSP without actual tests     

Heat transfer in power transistors

The internal heat transfer problem for a typical power-transistor structure has been solved analytically. The relations among current distribution, heat generation and temperature distribution have been derived. Usage of the resulting equations is illustrated by application to the most elementary problem, namely, uniform heat generation under the emitter.     

Recent developments in power transistors

Power transistors capable of providing five watts output are now in production. Because these units are relatively non-linear in their characteristics, large signal graphical analysis of their behavior is necessary. To facilitate this, the static characteristics of the grounded base, grounded emitter, and grounded collector circuits are presented for several temperatures. Since power transistors are seldom driven with a high impedance source, the input voltages must be known as well as the input currents. These characteristics are drawn to indicate both simultaneously on one chart. The power that must be removed from the junction of these transistors requires that the mounting for the transistor be thermally adequate to remove the heat without allowing the temperature of the Junction to exceed its critical value. The temperature power relationship is discussed and the theoretical size requirements for a heat dissipator are shown for free air convection and forced convection.     

Reliability study of power RF LDMOS device under thermal stress

This paper presents the results of comparative reliability study of two accelerated ageing tests for thermal stress applied to power RF LDMOS: Thermal Shock Tests (TST, air-air test) and Thermal Cycling Tests (TCT, air-air test) under various conditions (with and without DC bias, TST cold and hot, different extremes temperatures ΔT). The investigation findings of electrical parameter degradations after various ageing tests are discussed. On-state resistance (R_{ds_on}) is reduced by 12% and feedback capacitance (C_rss) by 24%. This means that the tracking of these parameters enables to consider the hot carrier injection as dominant degradation phenomenon. To reach a better understanding of the physical mechanisms of parameter's shift after thermal stress, a numerical device model (2D, Silvaco-Atlas) was used to confirm degradation phenomena.     

功率半导体IGBT热击穿失效的可靠性研究

针对变频空调使用缘栅双极型晶体管（IGBT）击穿短路故障进行分析,确认IGBT为过压损坏失效。,空调供电电源出现大的波动影响芯片供电电源质量,电压偏低导致IGBT开通异常,不能及时欠压保护,IGBT长时间处于工作在放大状态,IGBT开通损耗大热击穿失效。本文主要从电路设计,工作环境,模拟验证等方面分析研究,确认IGBT击穿短路失效原因,从设计电路与物料选型优化提升产品工作可靠性。     

Physical study of the dissipated power area in high electron mobility transistors for thermal modelling

The hot area in power transistors due to the power dissipation is determined from a 2D-hydrodynamic model. The power is calculated everywhere in the device from the knowledge of the physical quantities (current density, electric field). The hot area is determined accurately to be coupled to a thermal modelling giving the temperature everywhere in the device [J. Park, M.-W Shin, C.-C. Lee, Thermal modeling and measurement of GaN-based HFET devices, IEEE Electron Device Lett. 24(7) (2003) 424-426 [1]; J.-C Jacquet, R. Aubry, H. Gérard, E. Delos, N. Rolland, Y. Cordier, A. Bussutil, M. Rousseau, S.L. Delage, Analytical transport model of AlGaN/GaN HEMT based on electrical and thermal measurement, 12th GAAS Symposium, Amsterdam, 2004, pp. 235-238 [2].]. The method is applied to HEMTs (high electron mobility transistors) based on GaAs or GaN. It is shown that the hot area depends on the bias conditions and on the transistor gate recess topology.     

Reliability of amorphous InGaZnO TFTs with ITO local conducting buried layer for BEOL power transistors

The device reliability of a-IGZOTFTs with ITO local conducting buried layer (LCBL) has been investigated under positive gate bias stress and hot carrier stress for the application as BEOL power transistors. The drive current of a-IGZO TFTs could be controlled by the modulation of ITO LCBL thickness and distance under source/drain electrode. The threshold voltage shifts, the drain current degradation, and breakdown voltage have been measured and discussed according to the different ITO LCBL thickness and distance. The devices with thick ITO and short ITO distance are desirable for a power device for High/Low type I/O bridges. The devices with thin ITO and long ITO distance are desirable for Low/High type I/O bridges. The breakdown voltages are decreased with the increase of ITO thickness.     

Anomalous current distributions in power transistors

Current and temperature distributions of multi-emitter power transistors are analysed. The thermal properties, including thermal coupling, are described by a thermal resistance matrix. Anomalous current distributions over the emitter fingers which may lead to second breakdown are shown to be associated with the eigenstates of this matrix. Voltage and current-controlled second breakdown correspond to different eigenstates; the maximum power is inversely proportional to the relevant eigenvalue λ. The presence of emitter (or base) series resistance R gives rise to a thermal breakdown voltage BV_TH∞R/λ below which the device is always stable. The influence of the spacing between emitter fingers and of the quality of the thermal contact between chip and heat sink on the power handling capability is computed. Experimental evidence is presented which suppors the theory.