Short-channel C-MOS/SOS technology

Design, fabrication, and characterization of Si-gate short-channel C-MOS/SOS devices with channel length ranging from 1 to 3 µm are presented. Basic device parameters and their interrelations are discussed and illustrated in detail. Extremely-high-speed and low-power capability has been demonstrated for short-channel devices operating from a 5-V supply voltage. The process reproducibility and circuit performance point to the suitability of short-channel C-MOS/SOS technology for VLSI applications.     

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

There is one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines. The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid unexpected ESD damage on internal circuits. Experimental results show that it provides excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit. The device characteristics under a high-temperature environment of up to 150/spl deg/C are also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.     

CMOS放大器的温度补偿偏置

受载流子迁移率、阈值电压等参数的温度特性的影响，CMOS放大器往往具有较差的温度稳定性。本文介绍了一种基于恒跨导参考电流源偏置电路的温度补偿技术，理论分析和电路模拟结果显示，这种偏置方法对短沟道MOS管放大器也具有良好的温度补偿效果。     

Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

A technique for modeling the effect of variations in multiple process parameters on circuit delay performance is proposed. The variation in saturation current I_on at the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. The delay of a two-input NAND gate with 65 nm gate length transistors is extensively characterized by mixed-mode simulations, which is then used as a library element. Appropriate templates for the NAND gate library are incorporated in a general purpose circuit simulator SEQUEL. A 4-bit × 4-bit Wallace tree multiplier circuit, consisting of two-input NAND gates is used to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, by generating delay distributions, using an extensive Monte Carlo analysis. The use of linear interpolation and linear superposition is evaluated to study simultaneous variations in two and more process parameters. An analytical model for gate delays, in terms of device drive current I_on, is proposed, which can be used to extend this methodology for a generic technology library with a variety of library elements. The model is validated against Monte Carlo simulations and is shown to have a typical error of less than 0.1% for simultaneous variations in multiple process parameters. The proposed methodology can be used for statistical timing analysis and circuit simulation at the gate level.     

Physical basis of short-channel MESFET operation II: Transient behavior

The large-signal switching behavior of planar short-channel metal-semiconductor field-effect transistors (MESFET's) is simulated numerically. First, the intrinsic response of the MESFET is simulated in two space dimensions and time, using measured electric-field-dependent drift velocities and diffusivities in the conventional semiconductor equations; results of the intrinsic device simulations are then used to study the circuit behavior of Si and GaAs MESFET's in two-input NOR circuits. Although the simulated 1-µm-gate Si and GaAs MESFET's have intrinsic response times of 11 and 9 ps to a gate pulse of - 2 V, for fan-in and fan-out = 2, the Si and GaAs NOR gates have average gates delays of 318 and 118 ps, respectively, for 1-µm gate lengths. The power-delay products for these 1-µm-gate Si and GaAs circuits are 1.8 and 1.5 pJ, respectively. These results are compared with measured data and their physical basis is discussed.     

Accurate delay models for digital BiCMOS

A detailed transient analysis of the MOSFET-BJT combination prevalent in digital BiCMOS gates is presented. The analysis accounts for high-level injection leading to BJT β roll-off, base pushout leading to BJT f_T roll-off, short-channel behavior of the MOS drain current, and parasitic capacitances at the base and output. Based on the transient analysis, a piecewise delay expression is derived that shows excellent agreement with measured gate delay and with SPICE simulated delay. The comparisons are made for a wide range of circuit parameters in the gate, namely, MOSFET/BJT size, load capacitance, and supply voltage for both 1- and 0.6-μm BiCMOS technologies. The model is used to optimally size gates, and to determine circuit and device design guidelines to minimize the delay degradation at reduced supply     

Effects of source/drain implants on short-channel MOSFET I-V andC-V characteristics

The effects of source/drain implants on n-channel MOSFET I-V and C-V characteristics are measured and compared for the lightly doped drain (LDD) and the large-angle-tilt implanted drain (LATID) devices. We show that despite substantial improvement in hot-carrier reliability for LATID devices, the LATID design might have a limited range of application for short-channel MOSFETs. This is because as a result of enhanced V_TH roll-off and increased overlap capacitance for the LATID devices compared to LDD devices, the device/circuit performance degrades. The degradation of performance becomes more pronounced as device length is reduced. These results are confirmed by both experimental data and 2-dimensional numerical simulations     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

RFCMOS Unit Width Optimization Technique

In this paper, we demonstrate a unit width ( W_f) optimization technique based on their unity short-circuit current gain frequency (f_T) unilateral power gain frequency (f_MAX)? and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the W_f change is different; hence, some tradeoff is required to obtain the optimum W_f value. During the HF noise analysis, a new FOM is proposed to study the W_f effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in W_f does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistor's layout and helps to select the optimum Wf for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuit's performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum W_f for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies.     

Device physics and technology of complementary silicon MESFET's forVLSI applications

The development of a complete complementary MESFET technology is presented. The state-of-the-art, fully implanted, CMOS-like process uses Shannon implants together with a refractory silicide Schottky-gate material to combine high gate barrier heights with ease of fabrication. To minimize parasitic resistances, a unique sidewall structure and sidewall spacers are utilized to allow for self-aligned implantation of the source/drain regions. A self-aligned titanium silicidation technique is employed to minimize sheet and contact resistance of the source/drain regions. The SUPREM process simulator was employed extensively. The performance and modeling of device parameters (e.g., threshold voltage, gate leakage, and short-channel effects) and circuit parameters (e.g. standby current, noise margin, and speed) were accomplished through analytic formulations, the PISCES two-dimensional device simulator, and the SPICE circuit simulator     

Process/physics-based threshold voltage model for nano-scaled double-gate devices

Compact physics/process-based model for threshold voltage in double-gate devices is presented. Predominant short-channel effects for double-gate devices, which are drain-induced barrier lowering (DIBL) and short-channel-induced barrier lowering (SCIBL), are physically analysed and modeled to be applicable to SPICE-compatible circuit simulators. The short-channel models are also developed for bulk-Si device and compared to those of double-gate devices. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled L _eff = 25?nm double-gate devices and bulk-Si device.     

Double ion implanted V-MOS technology

An n-channel double ion implanted (or diffused] lateral V-MOS structure (D-V-MOS) for LSI digital application is presented. The effective channel is formed by the vertical difference in an n-type and a p-type impurity profile on a high resistive p-type substrate through a V-groove technique. Thus the threshold voltage and effective channel length of the D-V-MOS can be directly and accurately controlled by ion implantation. Very short-channel length (0.1 to 0.2 /spl mu/m) MOS devices with good electrical characteristics can thus be realized. A simple fabrication process with 5 masking steps for an n-channel self-isolated self-aligned enhancement/depletion (E/D) D-V-MOST device is presented. The fabrication procedures are described. Special features associated with the V structure are discussed. The short-channel effect is treated. It is found that the substrate sensitivity due to source-substrate biasing for a short-channel D-V-MOS is reduced significantly, even with a 1000-/spl Aring/ gate oxide thickness.     

Optimal Design of Triple-Gate Devices for High-Performance and Low-Power Applications

Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical $(hbox{n}^{+}/hbox{p}^{+})$ polysilicon gates. CMOS-compatible $V_{T}$'s for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.      

Deep-submicrometer large-angle-tilt implanted drain (LATID)technology

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology is described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n^- region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. A design that offsets the n⁺ implant by sidewall spacers to suppress the n⁺-gate overlap to zero while keeping the n^- region fully overlapped with the gate is found to be crucial for improved performance and reliability. The device performance, such as current drivability and short-channel effects, is described, and the circuit speed is investigated. Hot-carrier effects such as lateral electric field and device lifetime over a wide range of drain structures are also investigated. The tradeoff between device performance and hot-carrier reliability in deep-submicrometer LATID FETs is discussed     

Characterization and suppression of drain coupling in submicrometer EPROM cells

The EPROM transistor suffers from a capacitive-coupling-based short-channel effect called drain turn-on or Vdtothat limits the maximum drain voltage. Several measurement techniques are demonstrated to characterize the Vdtoeffect. An analytical model is applied to the problem to estimate the effects of process variations to suppress the phenomenon. The effect of Vdtoon scaling is discussed, and circuit and device design techiques to reduce or eliminate this problem are discussed.     

Short-channel effects in MOSFET's at liquid-Nitrogen temperature

Short-channel or high-field effects in MOSFET devices are a continuing area of research in room-temperature devices. Much has been learned in the past several years about the physical origins of these effects, and new or modified device structures have been proposed to minimize them. Because of the improved device and circuit performance possible at liquid-nitrogen temperature (LN2), there has been considerable recent interest in low-temperature device physics. While large-geometry MOSFET behavior has been discussed in the literature at LN2, very little has been quantified regarding short-channel effects at low temperature. This paper addresses the physical origins of short-channel effects at these temperatures. It is concluded that while the physical mechanisms are similar to those at room temperature, quantitative differences exist that favor LN2operation.     

Multiple-input logic circuit design using BiCMOS-based negative differential resistance circuits

We first propose an inverter circuit design using the negative differential resistance (NDR) circuit composed of the standard Si-based n-channel metal-oxide-semiconductor field-effect-transistor (NMOS) and SiGe-based heterojunction bipolar transistor (HBT). By suitably designing the MOS width/length parameters, we can obtain the ??-type NDR current?Cvoltage (I?CV) characteristic. Expanding the inverter circuit operation, the two-input and four-input NOR logic gates are demonstrated. Especially, the design and fabrication of the logic circuit is based on the standard SiGe BiCMOS process. Compared to the traditional NDR device like resonant tunneling diode (RTD), our MOS?CHBT?CNDR-based applications are much easier to be combined with some Si-based or SiGe-based devices on the same chip.     

A new and improved physics-based model for MOS transistors

An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.     

A CMOS-compatible rapid vapor-phase doping process for CMOS scaling

An advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 /spl Omega//sq has been realized. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1 /spl mu/m channel length and 40% higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and high-speed circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25 nm enables excellent dc and high-speed circuit performance in 0.1-/spl mu/m devices.     

Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS

Source/drain (S/D) engineering for ideal box-shaped junction formation using laser annealing (LA) combined with pre-amorphization implantation (PAI) is proposed and implemented in device integration for sub-100-nm CMOS on an SOI substrate. Modeling analysis for the resistance component associated with junction profile abruptness demonstrates that a noticeable reduction in parasitic series resistance with technology generation can be achieved through junction profile slope engineering. From the experimental results of LA, it is found that PAI not only controls the ultrashallow junction depth precisely, but also reduces the laser energy fluence required for impurity activation. In addition, laser annealing energy can be further reduced by use of SOI substrates in the device integration, indicating the implementation feasibility of LA to CMOS integration with an enlarged process window margin. The proposed S/D engineering is verified by the sheet resistance of junctions and the fabricated device current characteristics exhibiting substantially improved short-channel performance with higher current capability due to the box-shaped junction profile as compared with conventional rapid thermally-annealed (RTA) devices.