共查询到19条相似文献,搜索用时 187 毫秒
1.
本文结合抚钢引进50吨超高功率电弧炉注入电网谐波电流的预测及投产后谐波实测情况,分析了电弧炉运行时注入电网的谐波电流,介绍了电压畸变率的估算和测试方法。 相似文献
2.
如果一个检测周期内,不能有效检测具有内部缺陷严重的数字式避雷器,其高风险概率将不断升高,因此需要设计基于阻性电流测试的数字型避雷器内部缺陷检测系统,有效检测避雷器的内部缺陷。该系统利用数字化信号采集模块,采集避雷器泄漏电流的电信号并转换成光信号,光电变送器负责将接收的光信号转换为电信号,内部检测装置负责接收避雷器的泄漏电流数据;利用谐波分析法提取避雷器泄漏电流数据中的阻性电流基波分量,根据阻性电流基波分量的大小变化,判断避雷器的内部缺陷。实验证明,该系统采集的三相数字型避雷器泄漏电流波形准确性较高,能够有效检测数字型避雷器的内部缺陷。 相似文献
3.
吴才章 《自动化技术与应用》2009,28(6):74-75
基于短距离无线通信的便携式氧化锌避雷器在线测试仪由高压钳型电流传感器模块、绝缘操作杆和便携式主机三部分组成。高压钳型电流传感器模块夹在避雷器高压端或接地端,将采集到的泄漏电流信号调理放大,转化为数字信号,通过无线通信的方式将采集的信号传输到便携式主机;便携式主机通过无线方式接收高压钳型电流传感模块传送的数字信号,进行分析计算,得到氧化锌避雷器阻性电流的三次谐波含量,通过分析判断给出氧化锌避雷器的老化程度。 相似文献
4.
三相电网电压不对称时存在相位差,会影响电网运行的安全。为了对谐波的实时性及精度进行检测。提出一种改进的dq坐标变换的谐波和无功电流检测法:即用得到的对称性较好且频率与电网电压相同的基波正序电流或基波正序有功(无功)电流代替电网电压进行锁相得到dq变换所需的正余弦信号,避免了三相电压不对称带来的检测精度和实时性问题。利用MATLAB/SIMULINK仿真软件进行建模仿真,仿真结果表明,提出的方法提高了检测的精度和实时性,同时具有良好的动态响应速度及跟踪性能且实现简单、运用灵活。 相似文献
5.
6.
文中介绍了电压型STATCOM二重逆变电路结构,运用了PSCAD4.2.0对该类型STATCOM的电力系统进行仿真,分析了STATCOM直流侧电容参数对电网电流谐波含量的影响,得出了电网电流谐波含量随电容值变化的规律。着重分析了2次、11次和13次谐波与电容量的关系,提出了根据降低STATCOM出口端电流的谐波含量和保持直流侧电容电压波动幅值在一定范围内的要求来选择其电容值的方法。 相似文献
7.
8.
为解决电网中非线性负荷形成的无功电流和谐波电流对电网的影响,针对需为有源滤波器的控制提供谐波参考电流控制信号的特点,确定了谐波参考电流控制信号快速检测方法,并详细对谐波参考电流控制信号采用滑窗迭代DFT检测方法进行了理论分析,给出了谐波检测滑窗迭代算法软件流程图。MATLAB仿真结果证明,该方法简单可靠、实时性好、检测精度高。 相似文献
9.
10.
SVC产生的谐波电流较大,通常采用三角形联结的 TCR来抑制进入电网的三次谐波。当三相电压不平衡时,三次谐波电流不能构成零序系统而进入电网。论文提出一种抑制三次谐波电流方法,该方法采用三相晶闸管不对称触发来校正相电流,迫使每相三次谐波电流相等而不能进入电网。仿真结果验证了该方法的可行性。 相似文献
11.
在深入分析高压电网接地故障特征的基础上,阐释了适用于对各种电网中性点接地方式进行漏电保护的谐波方向原理,提出了一种谐波方向型高压电网选择性漏电保护的新方案。该方案以五次谐波分量作为研究重点,提取比较零序电压五次谐波信号,科学地分析电网故障,并进行相应的漏电保护。 相似文献
12.
The FINFET (Fin field-effect transistors) is projected as a favourable alternative to address challenges faced by continue scaling. Since nanometer procedure schemes are more advanced, the density of chip and frequency of operation have augmented, by making consumption of power in portable devices that are operated by battery could be a significant concern. Though for devices that are non-portable, the consumption of power is significant due to enhanced cooling & packaging costs and possible reliability issues. The metal oxide steady miniaturization semi-conductor field transistor by every novel generation of CMOS (Complementary Metal Oxide Semi-conductor) scheme enhances leakage currents because of minimum channel impacts. The power accounts that are in leakage has been enhancing in a large amount of total consumption of power in deep submicron schemes. Various strategies or schemes are proposes for lessening power leakage. Further, in a system on chip (SOC) designs, caches occupy a significant amount of area in DSP systems, leading to an increase in leakage power. Also, cache memories are used to store filter coefficients. Because of multiple gates, FINFETs structures have better electrostatic control over short channel effects, thus reduces leakage power effectively at the nano regime. In this paper, cache memory and FIR filter are designed by utilizing FINFETs at a 22-nanometer strategy utilizing HSPICE. The experimental outcomes exhibit that structures of FINFET have better leakage control over MOSFET and offers better performance. 相似文献
13.
The modern semiconductor industry is evolving quite rapidly. Portable and mobile devices are becoming smaller every day and there is also a growing demand for longer battery power. With these demands it is important for researchers to focus on the leakage power in stand-by mode. The SRAM was designed to accurately communicate with CPU, DSP, processor and low-power applications, such as battery-life handheld devices. For some days now, the design engineer focuses mainly on the production of large-capacity memories, high bandwidth and low energy consuming memories. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This Paper Describes the SRAM architecture designed for the reduction of power consumption or power leakages using sleep transistor and MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) techniques. This helps in the reduction of the CMOS transistor leakages. This paper incorporates multiple threshold strategies to give the proposed high speed, increased reliability and low leakage current of the updated 8T SRAM cell in stand-by memory cell mode. Based on the parameters like power dissipation at a different temperature, read voltage, write voltage, read delay, write delay, compared to the previously designed SRAM architecture of 6T, 7T, 8T and 13T we get low power consumption in our designed 8T SRAM architecture. The simulations are conducted with the UMC 55 nm technology Cadence Virtuoso method. 相似文献
14.
15.
16.
17.
This paper proposes an enhanced support vector machine (SVM), whose parameters are optimised by a novel mutant particle swarm optimisation (mutant PSO) algorithm to identify metal-oxide surge arrester conditions. The total leakage current and its resistive component under different arrester conditions are obtained and then are inputted into a multilayer SVM for the purpose of fault identification. Then, a mutant PSO-based technique is investigated to increase the classification accuracy as well as the training speed of the SVM classifier. The proposed technique has been tested on an actual data set obtained from Taipower Company to monitor five arrester operating conditions, including normal (N), pre-fault (A), tracking (T), abnormal (U) and degradation (D). Furthermore, to demonstrate the effectiveness of the proposed mutant PSO, the obtained results are compared to those obtained by using cross-validation method, genetic algorithm and particle swarm optimisation. 相似文献
18.
采用FFT算法对电网信号进行谐波分析时很难做到同步采样和整数周期截断,由此造成的频谱泄漏和栅栏效应将影响到谐波分析的结果。本文应用矩形窗和Hanning窗的加窗插值FFT算法分析非同步采样的电力系统谐波,经过MATLAB仿真证明:采用基于Hanning窗的加窗插值FFT算法能够大幅度降低由非同步采样造成的误差,最后给出了实现该算法的C语言程序。 相似文献
19.
《Journal of Systems and Software》1998,43(1):67-82
This article explores the major software systems used by MOSIS since its inception in 1980, developed by the author. The MOSIS project (Metal Oxide Silicon Implementation System) has served the nation by turning VLSI (microchip) designs, submitted over e-mail, into fully packaged chips, sent back to the user via US mail. Before MOSIS, chip designers were faced with a prohibitive fabrication expense, and the daunting tasks of augmenting their designs with various tedious geometries and coordinating the various vendors ranging from mask making for the fabrication of silicon to packaging. The major innovation has been the “sharing of silicon”. The various “packers” that implement silicon sharing are explored, as well as the other requisite software. 相似文献