Amorphous silicon buried-channel thin-film transistors

We demonstrate a buried-channel thin-film field effect transistor (TFT) based on deposited silicon nitride and hydrogenated amorphous silicon with the conducting channel recessed approximately 50 Å from the interface. We fabricate transistors and capacitors by DC reactive magnetron sputtering of a silicon target in a plasma of (Ar+H ₂+N₂) or (Ar+H₂) for the nitride and silicon layers, respectively. To create a step in the conduction band, and thus a buried-channel, we vary the hydrogen partial pressure which varies the hydrogen content and the bandgap of amorphous silicon. Capacitance-voltage and current-voltage measurements on these devices present strong evidence for the existence of the buried-channel. We achieve a record field effect mobility in saturation of 1.68 cm² /V-s with amorphous silicon deposited at 230°C, and an acceptable mobility of 0.44 cm²/V-s with amorphous silicon deposited at 125°C     

Poly-Si thin-film transistors on steel substrates

We report the successful fabrication of poly-Si thin-film transistors (TFTs) on stainless steel substrates. The TFTs were fabricated on a 500 μm thick polished stainless steel substrate using furnace crystallized amorphous Si deposited by PECVD. These devices typically have threshold voltages of 8.6 V, linear effective mobilities of 6.2 cm²/V·s and subthreshold slopes of 0.93 decade/V. This work demonstrates the feasibility of poly-Si TFTs on stainless steel substrates and identifies some critical issues involved in poly Si processing on stainless steel. This will enable the fabrication of arrays with integrated drivers on a cheap, flexible and durable substrate for various displays and other large area array microelectronic applications     

Amorphous silicon thin-film transistors on compliant polyimide foilsubstrates

Much of the mechanical strain in semiconductor devices can be relieved when they are made on compliant substrates. We demonstrate this strain relief with amorphous silicon thin-film transistors made on 25-μm thick polyimide foil, which can be bent to radii of curvature R down to 0.5 mm without substantial change in electrical characteristics     

Complementary metal-oxide-semiconductor thin-film transistor circuits from a high-temperature polycrystalline silicon process on steel foil substrates

We fabricated CMOS circuits from polycrystalline silicon films on steel foil substrates at process temperatures up to 950/spl deg/C. The substrates were 0.2-mm thick steel foil coated with 0.5-/spl mu/m thick SiO/sub 2/. We employed silicon crystallization times ranging from 6 h (600/spl deg/C) to 20 s (950/spl deg/C). Thin-film transistors (TFTs) were made in either self-aligned or nonself-aligned geometries. The gate dielectric was SiO/sub 2/ made by thermal oxidation or from deposited SiO/sub 2/. The field-effect mobilities reach 64 cm/sup 2//Vs for electrons and 22 cm/sup 2//Vs for holes. Complementary metal-oxide-silicon (CMOS) circuits were fabricated with self-aligned TFT geometries, and exhibit ring oscillator frequencies of 1 MHz. These results lay the groundwork for polycrystalline silicon circuitry on flexible substrates for large-area electronic backplanes.     

Polysilicon thin-film transistors on polymer substrates

Different approaches to fabricate low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) on polymer substrates are reviewed and the two main routes are discussed: (1) standard fabrication of LTPS TFTs on glass substrates followed by a transfer process of the devices on the polymeric substrate; (2) direct fabrication of the devices on the polymeric substrate. Among the different techniques we have described in more detail the process we have recently developed for the fabrication of LTPS TFTs directly on ultra-thin polyimide (PI) substrate. LTPS TFT technology is particularly suited for high performance flexible electronics applications, due to the excellent device characteristics, good electrical stability and CMOS technology. Flexible display application remains the most attractive application for LTPS technology, especially for AMOLED displays, where device stability and the possibility to integrate the driving circuits make LTPS technology superior to all the other competitive TFT technologies. Among the other applications, particularly promising is also the application to flexible smart sensors, where integration of a front-end electronics is essential. Some examples of flexible gas sensors and pressure sensors, integrated with simple readout electronics based on LTPS TFTs and fabricated on ultra-thin PI substrate, are presented.     

Electrographically patterned thin-film silicon transistors

The authors made amorphous silicon thin-film transistors on glass foil using exclusively electrophotographic printing for pattern formation, contact hole opening and device isolation. Toner masks were applied by feeding the glass substrate through a photocopier, or from laser-printed patterns on transfer paper, This all-printed patterning is an important step toward demonstrating a low-cost large-area circuit processing technology     

Novel profiled thin-film polycrystalline silicon solar cells onstainless steel substrates

In order to obtain higher conversion efficiencies while keeping the manufacturing cost low in thin-film PV technologies, a possible low bandgap material is amorphous silicon germanium. Although record efficiencies in excess of 15% have been reported for triple-junction solar cells comprising these alloys, concerns regarding the stability and quality of this material still need to be overcome. Another approach is the introduction of thin-film micro- or polycrystalline silicon with a band gap of 1.1 eV, deposited at a temperature that is low enough to allow cheap, “foreign” carrier materials. Apart from the application of a modified PECVD method utilizing frequencies in the VHP domain, the hot wire CVD (HWCVD) method appears a particularly promising technique for the deposition of high-quality thin-film intrinsic or doped poly-Si. In this contribution, special attention will be paid to the latest developments in the application of hot-wire deposited silicon thin films in solar cells. By implementing a profiled hydrogen-diluted HWCVD growth scheme that produces a thin small-grained seed layer on top of a thin n-layer, we have been able to obtain fast polycrystalline growth of the intrinsic layer of an n-i-p solar cell. An efficiency of 4.41% is obtained and the fill factor is 0.607. The current density is close to 20 mA/cm² for an i-layer that is only 1.22 μm thick. The cell is deposited on plain stainless steel and thus does not comprise a back reflector     

Electrophotographic patterning of thin-film silicon on glass foil

We report the patterning of thin films of amorphous silicon (a-Si:H) using electrophotographically applied toner as the etch mask. Using a conventional xerographic copier, a toner pattern was applied to 0.1 μm thick a-Si:H films deposited on ~50 μm thick glass foil. The toner then served as the etch mask for a-Si:H, and as the lift-off material for the patterning of chromium. This technique opens the prospect of roll-to-roll, high-throughput patterning of large-area thin-film circuits on glass substrates     

Polycrystalline silicon thin-film transistors with two-stepannealing process

Thin-film transistors (TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature furnace annealing and high-temperature rapid thermal annealing leads to a significant improvement in the material quality. The TFTs obtained with this two-step annealing material exhibit better measured characteristics than those obtained by using conventional furnace annealing     

Inverter circuits on glass substrates based on ZnO-nanoparticle thin-film transistors

The integration technique and the properties of inverter circuits on glass substrates using ZnO nanoparticles as semiconductor material are presented. The inverter device consists of a switching and a load metal–insulator–semiconductor field-effect transistor with poly(4-vinylphenol) as the gate dielectric. Although the semiconductor is deposited by spin-coating of a colloidal ZnO dispersion and the process temperature is limited to 200 °C, the inverters show reasonable maximum peak gains at low power consumption. The maximum peak gain was 6 V/V, whereas the maximum static power dissipation density was less than 26 nW/μm². Additionally, the influence of the geometry ratio as well as of the supply voltage on the device performance has been investigated. With regard to the optical characteristics, the proposed technique leads to circuits with an optical transmittance of up to 80%.     

Effects of gamma-ray irradiation on polycrystalline silicon thin-film transistors

The effects of gamma-ray irradiation on the performance of polycrystalline silicon thin-film transistors are investigated. After irradiation, the threshold voltage of the TFTs is shifted negatively and well-defined kinks are formed in the subthreshold regions of the transfer characteristics, explained by the turn-on of back channel and sidewall leakage current paths. In the non-irradiated device, the leakage current I_L is controlled by the reverse biased drain junction, while after irradiation I_L is limited by the intrinsic resistance of the polysilicon material itself.     

Low-temperature materials and thin-film transistors for electronics on flexible substrates

The deposition processes and electronic properties of thin-film semiconductors and insulators based on silicon in relation to the fabrication of electronic devices on flexible plastic substrates are considered. The films of amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN_x), and also thin-film transistors are fabricated at comparatively low temperatures (120°C, 75°C) using existing commercial plasma-chemical equipment. The parameters of thin-film transistors based on a-Si:H and fabricated at the aforementioned relatively low temperatures are compatible with those of high-temperature analogues.     

Hysteresis effect in bottom-gate polymorphous silicon thin-film transistors

The hysteresis effect observed in the transfer characteristics of n-channel bottom-gate hydrogenated polymorphous silicon (pm-Si:H) thin-film transistors (TFTs) is investigated in terms of the channel width. Such phenomenon is observed in devices of wide channel (>20 μm), whereas it diminishes in devices of narrow channel. The hysteresis of wide channel TFTs is mainly due to charges injected from the channel, trapped in the gate dielectric. As the channel width is reduced the edge effect becomes more significant and the effect of carrier injection from the channel is eliminated, which is balanced by the effect of charge injection from the gate electrode.     

High-performance thin-film silicon-on-insulator CMOS transistors inporous anodized silicon

Ultrathin-film silicon-on-insulator (SOI) CMOS transistors, produced in silicon islands 100 nm thick, formed by oxidation of porous anodized silicon, are described. Both n-channel and p-channel mobilities are similar to equivalent bulk values. Subthreshold slopes are less than 80 mV/decade and junction leakages are approximately 0.1 pA/μm. No kink is seen in the output characteristics of the n-channel transistors as the silicon film is fully depleted. A ring-oscillator gate delay of 161 ps has been achieved, at a power dissipation of 270 μW/stage, for 1.5-μm gate length     

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors (TFTs) with different channel lengths were realized. The NMOS enhancement load saturation mode (NELS) inverters were prepared by plasma-enhanced chemical vapor deposition at temperatures below 200 °C. The realization of microcrystalline silicon thin-film inverters facilitates the direct integration of column and row drivers and circuitry on display backpanels. The influence of the transistor properties and underlying contact effects on the performance of the inverters will be discussed.     

Dimensional effects on the reliability of polycrystalline silicon thin-film transistors

We found that for unpassivated short-channel TFTs, hot carrier stress-induced degradation phenomena are different with various channel geometries. For device with a wide channel width, the threshold voltage is increased while the subthreshold swing is almost unchanged. The stress-induced oxide-trapped charges are responsible for the degradation. For others with narrow channel widths after stress, on the contrary, the subthreshold swing and I_min are increased, the trap density is greatly increased and the trap-enhanced kink effect is also observed. This is due to the generation of stress-induced grain boundary traps near the drain side. Additionally, the stress-induced degradations of passivated TFTs with various geometries are identical. The increased defect density dominates the mechanism since the hot-carrier stress tends to break the passivated Si-H bonds.     

Recent advances in thin-film silicon devices on sapphire substrates

The growth of silicon films on insulating substrates, their fabrication into active devices, and the advantages of such devices, especially for fast memory applications, were previously reported. Recent advances in these devices are described, including techniques of material growth and characterization, fabrication procedures, and device results. Thin-film resistors and capacitors operating at UHF have been prepared. With improvements in the material and device processing, bipolar transistors with current gains of 20-40 and useful operation between 500 and 1000 MHz were fabricated. MOS triodes and tetrodes which operate at the same frequency range and silicon-gate MOSFETs (SIGFETs), with voltage gains between 50-150 having negligible feedback capacitances (less than 0.02 pF/electrode), have been made. Thresholds of 1.5 and 2.5 V for p- and n-type devices were obtained. Application of these devices for microwave ICs and subnanosecond switching networks are described.     

Polycrystalline silicon thin-film transistors fabricated by defect reduction methods

Fabrication of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) at a low temperature is reported. 13.56 MHz-oxygen plasma at a 100 W, 130 Pa at 250/spl deg/C for 5 min, and heat treatment at 260/spl deg/C with 1.3/spl times/10/sup 6/-Pa-H/sub 2/O vapor for 3 h were applied to reduction of the density of defect states in 25-nm-thick silicon films crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Defect reduction was numerically analyzed. Those treatments resulted in a high carrier mobility of 830 cm/sup 2//Vs and a low threshold voltage of 1.5 V at a laser crystallization energy density of 285 mJ/cm/sup 2/.     

Air-gap polycrystalline silicon thin-film transistors for fully integrated sensors

Air gap thin-film transistors (TFTs) were fabricated using a solid phase crystallization process. Undoped polycrystalline silicon (polysilicon) was used as the active layer and a highly doped polysilicon bridge was used as the gate, which promotes the air gap. These TFTs have comparable threshold voltage (V/sub T/) and subthreshold slope characteristics to TFTs fabricated using pulsed laser crystallization, and using silicon dioxide as gate insulator. The low value of V/sub T/ is very important for low power consumption. Moreover, the air-gap TFT fabrication process is compatible with low-temperature glass substrate technology, which allows the integration of sensors and electronics circuits.     

On the conduction mechanism in polycrystalline silicon thin-film transistors

Physical and electrical analyses were carried out on n-channel polycrystalline silicon thin-film transistors (nTFTs) with active regions as thin as approximately 6 nm. Such thin active regions extinguish the dominating effects of anomalous leakage and allow the conduction energy barrier height to be analyzed as a function of gate voltage in the femtoampere source/drain current regime. Grain size statistics were determined using plan view transmission electron microscopy. It is shown for the first time that in the absence of anomalous leakage, the barrier height does not decrease with decreasing gate voltage. In addition, the maximum measured barrier height is almost independent of active region thickness and grain size statistics. The source/drain current at low lateral field and high vertical field is also independent of channel length for all devices with length varied over an order of magnitude. These important discrepancies with existing TFT conduction theory are discussed within a physics-based model that addresses the effects of disorder-induced localized electron states in the bandgap. Besides describing existing data and well-known TFT behavioral trends, the model predicts a previously unknown relationship between threshold voltage variation, average threshold voltage and the number of grains in the channel. Analysis of data gathered from hundreds of devices of different dimensions across three different grain size distributions not only leads to agreement with the model but also to a remarkable universal behavior linking electrical and physical properties. This study shows the physics of polycrystalline silicon TFT conduction to be of the same form as amorphous and single crystal devices with the degree of disorder as the sliding scale between the two extremes.