实时时钟芯片DS1302在DSP嵌入式系统中的应用

在许多嵌入式应用场合需要实时时钟的功能,通常DSP（数字信号处理器）芯片并不具备此功能,因此在实际使用过程中需要外扩实时时钟芯片来解决该问题。文中介绍了串行时钟芯片DS1302的功能以及在DSP嵌入式实时处理系统中的应用,给出了基于CPLD（复杂可编程逻辑器件）的控制器逻辑设计和DSP底层软件驱动编写的方法,指出了逻辑设计中需要注意的问题。实现一种分层、高效和可移植的嵌入式系统。经过长期的试验．实时时钟运行稳定准确,取得了良好的效果。     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

基于片上系统的时钟复位设计

从方法优化和电路设计入手,提出了基于片上系统(SOC)的复位方法和时钟复位电路.设计了片外按键复位电路、片内上电电路、晶振控制电路、片内RC低频时钟电路、槽脉冲产生电路、分频延时电路、时钟切换电路及异步复位同步释放电路等电路模块.以上电路模块构成了片上系统的时钟复位电路,形成了特定的电路时钟复位系统.该时钟复位系统将片外按键复位与片内上电复位结合起来,形成多重复位设计,相比单纯按键复位更智能,相比单纯上电复位则更可靠.另外,该时钟复位系统还采用了片内RC振荡时钟电路等一系列电路,借助片内RC时钟实现对芯片的延时复位,进而在保证复位期间寄存器得到正确初始化的同时,还使得芯片能够始终处在稳定的晶振时钟下正常工作.相比传统的时钟复位电路,该时钟复位系统既便捷,又保证了系统初始化和系统工作的可靠性.     

一款32位定点DSP电路的设计

文章通过对32位定点DSP的体系结构及其设计方法的研究,重点阐述了32位定点DSP中CPU包括ALU、MPY、ARAU、流水线、指令系统和总线接口等关键逻辑部件工作原理,对各个逻辑部件的设计思路和实现方法进行了分析描述。采用基于标准单元正向设计方法,设计了一款32位指令集的定点DSP电路,该电路采用哈佛总线结构,可以在单周期内实现16×16位有符号整数乘法、32位累加和32位数据的算术逻辑运算,处理精度高。该电路采用0.5μm 1P3M CMOS工艺流片,集成度7万门,工作频率可达36 MHz,动态功耗594 mW。     

A 32-b RISC/DSP microprocessor with reduced complexity

This paper presents a new 32-b reduced instruction set computer/digital signal processor (RISC/DSP) architecture which can be used as a general purpose microprocessor and in parallel as a 16-/32-b fixed-point DSP. This has been achieved by using RISC design principles for the implementation of DSP functionality. A DSP unit operates in parallel to an arithmetic logic unit (ALU)/barrelshifter on the same register set. This architecture provides the fast loop processing, high data throughput, and deterministic program flow absolutely necessary in DSP applications. Besides offering a basis for general purpose and DSP processing, the RISC philosophy offers a higher degree of flexibility for the implementation of DSP algorithms and achieves higher clock frequencies compared to conventional DSP architectures. The integrated DSP unit provides instruction set support for highly specialized DSP algorithms. Subword processing optimized for DSP algorithms has been implemented to provide maximum performance for 16-b data types. While creating a unified base for both application areas, we also minimized transistor count and we reduced complexity by using a short instruction pipeline. A parallelism concept based on a varying number of instruction latency cycles made superscalar instruction execution superfluous     

基于DSP开发系统设计与实现

为了设计一个性能稳定的DSP开发系统,利用TI公司最新推出的TMS320F28335作为微处理器,该芯片为32位浮点型DSP。在采用浮点DSP设计系统时,不需要考虑处理的动态范围和精度,比定点DSP在软件编写方面更容易,更适合采用高级语言编程。外围电路主要包含电源电路、RAM扩展电路、晶振电路和复位电路,用来辅助DSP的工作。利用电源管理芯片设计电源电路,可以有效解决其他型号的DSP对上电顺序的要求;扩展的外部RAM可以使程序的调试与下载更加方便。利用外部时钟源作为时钟输入,使其输入时钟更加稳定的同时,也可为具有相同时钟的多个DSP使用。利用三端监控芯片来实现系统的手动复位和自动复位,使系统的稳定性大大提高。     

Clock frequency and latency in synchronous digital systems

The tradeoffs in the design of synchronous digital systems between clock frequency and latency in terms of the circuit characteristics of a pipelined data path are described. A design paradigm relating latency and clock frequency as a function of the level of pipelining is developed for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems which describe these performance parameters in terms of the delays of the logic, interconnect, registers, clock skew, and the number of logic states. These results provide an approach to the design of those synchronous digital systems in which latency and clock frequency are of primary importance. From the behavioral specifications for the proposed system, the designer can use these results to select the best logic architecture and the best available device technology to determine if the performance specifications can be satisfied, and, if so, what design options are available for optimization of other system attributes, such as area     

用FIFO设计A/D与DSP之间的接口

在采用CCD对非透明薄板厚度的测量系统设计中，采用高速A／D和DSP等器件进行电路设计可以确定CCD的像点位置。由于A／D转换器的采样速率和DSP的工作时钟频率相差非常大，为了提高DSP的工作效率，避免数据丢失和控制方便，采用小容量的FIFO作为两者之间的接口可以产生很好的效果。     

Mixed static and domino logic on the CMOS gate forest

In a semicustom design environment with unified transistor geometries, logic circuit optimization is achieved using an efficient physical circuit implementation. In particular, the semicustom realization of domino logic is demonstrated with a standard-cell and a multiplier design which are used to support the implementation of such a dynamic logic design style on a gate forest, which has a higher n count than p count. The mixture of complementary and dynamic logic allows the designer to improve the critical-path delay and to reduce the size of the layout. The domino standard-cell architecture supports multiple-output configurations and additional internal precharge. The operation time for a mixed static/dynamic multiplier is approximately 30% higher than that of the static version based on a carry select adder. This difference mainly affects the critical delay of the sign-extension path of the parallel adder array     

A 32-bit VLSI digital signal processor

A general-purpose programmable digital signal processor (DSP) has been implemented in 1.5-/spl mu/m (L/SUB eff/) NMOS technology using full-custom circuit design for high performance. The DSP has a 32-bit instruction set, 32-bit data path, and full-hardware 32-bit floating-point arithmetic. The architecture is described section by section, and an overview of the instruction set is presented. The extensive design verification process applied to the DSP is also described.     

全数字延时锁定环及其应用

介绍了一种区别于锁相环(PLL)和基于压控延迟线(VCDL)的延时锁定环(DLL)、全部由纯数字电路实现的DLL电路.该电路用于消除时钟时延,全数字的结构使其无条件稳定,不会累积相位误差,而且具有良好的噪声敏感度、较低的功耗和抖动性能.使其在时延补偿和时钟调整的应用中具有优势,并可全部嵌入单个芯片中.文中分析了全数字DLL的工作原理及其结构,给出了其在现场可编程门阵列(FPGA)中的应用.     

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI

A 300-MHz 16-b fixed-point digital signal processor (DSP) core LSI has been developed for video signal processing. In order to achieve high performance, the DSP core LSI employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design. The DSP core LSI, which was fabricated with 0.5-μm BICMOS and triple-level-metallization technology, has a 3.9 mm×4.6 mm area, and contains about 57K transistors. It consumes 2 W at a 300-MHz clock frequency with a 3.3-V power supply. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively     

A Low Power Approach to Floating Point Adder Design for DSP Applications

The demand for high performance, low power floating point adder cores has been on the rise during the recent years particularly for DSP applications. In this paper, we present a new architecture for a low power, IEEE compatible, floating point adder, that is fast and has low latency. The functional partitioning of the adder into three distinct, clock gated data paths allows activity reduction. The switching activity function of the proposed adder is represented as a three state FSM. During any given operation cycle, only one of the data paths is active, during which time, the logic assertion status of the circuit nodes of the other data paths are held at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and pseudo leading zero anticipatory logic as well as data path simplifications. In contrast to conventional high speed floating point adders that use leading zero anticipatory logic, the proposed scheme offers a worst case power reduction of 50%.     

FPGA实现高速FFT处理器的设计

介绍了采用Xilinx公司的Virtex -II系列FPGA设计高速FFT处理器的实现方法及技巧。充分利用Virtex -II芯片的硬件资源 ,减少复杂逻辑 ,采用流水方式对复数数据实现了加窗、FFT、求模平方三种运算。整个设计采用流水与并行方式尽量避免瓶颈的出现 ,提高系统时钟频率 ,达到高速处理。实验表明此处理器既有专用ASIC电路的快速性 ,又有DSP器件的灵活性的特点 ,适合用于高速数字信号处理     

嵌入式Flash CISC/DSP微处理器的研究与实现

本文研究一种新的既具有微控制器功能,又有增强DSP功能的高性能微处理器的实现架构.在统一的增强CISC指令集下,我们将基于哈佛和寄存器-寄存器结构的微处理器模块和单周期乘法/累加器、桶形移位寄存器、无开销循环及跳转硬件支持模块、硬件地址产生器等DSP功能模块以及嵌入式Flash Memory和指令队列缓冲器有机的集成起来,在统一架构下通过单核实现CISC/DSP微处理器,有效地提高了处理器的性能.该微处理器采用0.35μm CMOS工艺实现,芯片面积为25mm².在80M工作频率下,动态功耗为425mW,峰值数据处理能力可达80MIPS.该处理器核可满足片上系统(SOC)对高性能处理器的需求.     

Synchronous mirror delay for multiphase locking

A clock generation circuit having the function of multiphase locking was designed using the synchronous mirror delay (SMD) scheme. The internal clock can be synchronized to the external clock with intended phase difference. The synchronizing error of the clock generation circuit is reduced below the delay time of unit delay stage by compensation characteristics of detecting circuit in SMD. A 32-M double data rate (DDR) SRAM including the clock generation circuit is fabricated using 0.13-/spl mu/m CMOS technology. To measure the synchronizing error of the clock generation circuit, the test elements group (TEG) system is designed and fabricated with the main system. The synchronizing error of the clock generation circuit is far smaller than the delay time of unit delay stage at zero phase locking and similar to the delay time of unit delay stage at multiphase locking.     

A 32 kbyte integrated cache memory

The system, circuit, layout and device levels of an integrated cache memory (ICM), which includes 32 kbyte DATA memory with typical address to HIT delay of 18 ns and address to DATA delay of 23 ns, are described. The ICM offers the largest memory size and the fastest speed ever reported in a cache memory. The device integrates a 32 kbyte DATA INSTRUCTION memory, a 34 kbit TAG memory, an 8 kbit VALID flat, a 2 kbit least recently used (LRU) flag, comparators, and CPU interface logic circuits on a chip. The inclusion of the DATA memory is crucial in improving system cycle time. The device uses several novel circuit design technologies, including a double-word-line scheme, low-noise flush clear, a low-power comparator, noise immunity, and directly testable memory design. Its newly proposed way-slice architecture increases both flexibility and expandability     

Design and optimization of buffer chains and logic circuits in aBiCMOS environment

The design and optimization of BiCMOS buffer chains and multi level logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multi level CML (current mode logic) gates is also studied     

Instantaneous Clockless Data Recovery and Demultiplexing

An alternative architecture for instantaneous data recovery for burst-mode communication is introduced. The architecture can perform 1:$n$demultiplexing without additional clock recovery phase-locked loop or sampling blocks. A finite-state machine (FSM) is formed with combinational logic and analog LC transmission line delay cells in a feedback loop. The FSM responds to input data transitions instantaneously and sets the outputs. The system reduces unit interval jitter by a factor of$n$. The new architecture is demonstrated via a SiGe 1:2 clockless demultiplexer circuit that operates at 7.5 Gb/s.     

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Negative Bias Temperature Instability (NBTI) in pMOS transistors has become a major reliability concern in the state-of-the art digital circuit design. This paper discusses the effects of NBTI on 32 nm technology high fan-in dynamic OR gate, which is widely used in high-performance circuits. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG), are analyzed in the presence of NBTI degradation. We have shown the degradation in the output inverter pMOS transistor of the domino gate has a dominant impact on the delay in comparison with the keeper impact. Based on this analysis we have proposed that upsizing just the output inverter pMOS transistor can compensate for the NBTI degradation. Moreover, the impact of tuning the duty cycle of the clock has been investigated. It has been shown that although the keeper and the precharge transistors experience more NBTI degradation by increasing the low level in the clock signal, the total performance of the circuit will improve. We have also proposed an adaptive compensation technique based on Forward Body Biasing (FBB), to recover the performance of the aged circuit.