A 32-bit logarithmic number system processor

To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log₂(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 2^0.x function. The basic concept behind DP is that variablex can be divided into two parts in bit representation to be implemented. Thus, ROM or PLA table can be reduced to a reasonable size and this will make a high precision design allowable. The basic idea of IDLA is that the function 2^0.x can be obtained approximately through iterative linear approximations. By this method, only adder, shifter and a small PLA are required, unlike the previous designs which require ROM and multiplier. The experiment results reveal that the proposed design is more attractive than the previous researches in the LNS processor.This work was supported by the National Science Council under Grant NSC 84-2215-E002-020.     

A 300-MHz 16-b BiCMOS video signal processor

A 300-MHz 16-b full-programmable parallel-pipelined video signal processor ULSI has been developed. With multifunctional arithmetic units to achieve parallel vector processing, and with a phase-locked-loop (PLL) type clock generator to help attain the 300-MHz internal operating speed, this ULSI is able to attain, with only one chip, 30-frame-per-second full-CIF video data coding based on CCITT H.261. Two different types of pass-transistor BinMOS circuits have been developed to help achieve an access time of 3 ns for a 146-kb SRAM and for data buses. Fabricated with a 0.5-μm BiCMOS and triple-layer metallization process technology, the video signal processor ULSI contains 1.27-million transistors in a 16.5×17.0-mm² die area     

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0-μm CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment     

The 68040 32-b monolithic processor

A 32-b single-chip processor has been developed that is user object-code compatible with members of the 68000 processor family. The 14-4-mm×15.5-mm device contains over 1.2 million transistors and is fabricated with a double-layer-metal CMOS process. The processor integrates three major functional units: an integer processor: a floating-point processor; and a Harvard-style memory unit. Each major unit is described, and the implementation techniques that were employed and selected circuit issues that were confronted in the design are discussed     

The multipurpose integrated electronic processor

At the University of Ottawa, a Multipurpose Integrated Electronic Processor (MIEP) is being built for basic research in integrated electronics and its related fields. When completed, the MIEP will permit controlled deposition of thin films, electron-beam micromachining, topological inspection and chemical analysis of the films. These processes will be achieved without the need of moving the substrate from one chamber to another, with the associated problems of reregistration and maintaining clean surfaces. The primary aim of the project is the fabrication of thin-film integrated circuits containing micron-sized active and passive elements.     

A 30-MHz mixed analog/digital signal processor

A multiplying encoder architecture that is implemented in the design of a mixed analog and digital signal processor is presented. The processor is suitable for performing both high-speed A/D conversion and digital filtering in a single chip. The device can resolve the input with 8 b at 30 Msample/s and perform 28 multiply and 28 add operations per sample under typical conditions. The processor is designed for a 28-tap programmable FIR (finite impulse response) filter with analog input signal which can be used for waveform shaping of the modem to obtain the desired transmission performance for business satellite communication and mobile communication. The chip is fabricated in a 1-μm double-polysilicon and double-metal CMOS technology. The chip size is 9.73×8.14 mm², and the chip operates with a single +5.0-V power supply. Typical power dissipation is 950 mW; 330 mW is dissipated in analog and 620 mW is in the digital block     

A 9-b charge-to-digital converter for integrated image sensors

Charge-to-digital conversion offers advantages over conventional charge readout techniques because it performs digitization directly in the charge domain. The approach consolidates hardware, reduces power and weight, and eliminates many sources of noise and nonlinearity. This paper introduces an architecture for a charge-to-digital converter (CDC) that is tailored toward a charge-coupled device (CCD) implementation. New methods of generating charge, sensing charge, and comparing charge packets are described that improve conversion accuracy. Factors limiting device performance are discussed. Measured results are presented for two prototype CDCs. The first, using buried channel CCDs, is optimized for resolution. It achieves 56 dB spurious free dynamic range (SFDR) at a 2 MHz sampling rate and operates from 5 V. The second, using surface channel CCDs, is optimized for power and speed. It achieves 49 dB SFDR at a 15 MHz sampling rate and consumes 13 mW power at its maximum sampling rate of 22 MHz     

2-D digital filters using logarithmic number systems

The letter deals with the design of 2-D digital filters to be implemented in a logarithmic number system. The accuracy of the coefficient representation is considered, and a limit on the maximum useful word length is derived. An optimisation procedure is proposed, together with a few examples of 2-D filter design.     

An 80-MOPS-peak high-speed and low-power-consumption 16-b digitalsignal processor

This paper describes a 16-b fixed point digital signal processor (DSP), especially its multiply-accumulate (MAC) unit, memories, and instruction set. By adopting a redundant binary multiplier and a variable pipeline structure, this DSP's MAC unit, compared to a conventional MAC unit, consumes about 15% less power and operates 24% faster. Furthermore, its double-speed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power. By being able to more finely control which portions of memory are activated, the data ROM and data RAM's precharge current was reduced to about 1/8 of the conventional ROM and RAMs. We redesigned the instruction set and reduced its width from 32 b to 24 b based on the analysis of data generated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory size 33% smaller than the previous one. This chip is fabricated with a 0.5-μm double-metal-layer CMOS process and achieves 80-MOPS-peak double speed multiply-accumulate performance     

A new carry-free division algorithm and its application to asingle-chip 1024-b RSA processor

A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm² in a 2-μm CMOS process and 500 mW at 25 MHz)     

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP)ULSI

The first single-chip 64-b vector-pipelined processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage pipelined adder/shifter, a 64-b five-stage pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8-μm BiCMOS and triple-layer metallization process technology, has a 17.2-mm×17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply     

综合核心处理机的设计与实现

针对机载传感器系统的数字计算应用,分析了综合核心处理机（ICP）的架构特征及其设计时的考量因素,完成了软硬件架构及总线互连设计。在保证ICP硬件通用化、架构开放性及功能可重构的前提下,通过合理地设计模块内部电路、软件层次、网络拓扑及传输机制,有效降低了通信代价,从而提高系统的运算性能。这些方法和技术已被证明是可行的,并在实际的工程中成功应用。     

针对客户前端设备的集成通信处理器RC32355

适用于小型企业和家庭的新型通信设备正在形成一个具有巨大潜力的市场。随着多PC环境的普及,家庭/小型办公室网络的需求增长,网络连接的新设备开始出现,它们可以在广域网(WAN)接口和局域网(LAN)接口之间提供桥接。市场上流行着多种技术,存在着相互竞争的标准。IDT公司作为一家专门为推动语音、数据和无线网络统一的新型通信企业提供     

30-Msamples/s programmable filter processor

A 30-MHz finite impulse response (FIR) programmable filter processor that has been developed using a 1.2-μm CMOS EPROM technology with single metal is discussed. Its 30-MHz worst-case operating frequency meets most video filtering requirements and demonstrates the potential of nonvolatile memory technologies in embedded applications. The processor has been designed with a high level of parallelism and pipelining by using a transposed FIR structure. In this approach, the multipliers are implemented with an EPROM-based look-up table containing the results of the products between video samples and filter coefficients, according to the user's application. The chap can implement every kind of FIR filter with a maximum complexity of 59 taps in a half-band filter configuration, 32 taps for a symmetric filter, and 167 taps for an asymmetric one. The equivalent coefficient precision is 12 b, assuming 8 b of input data precision. Multiprocessor configurations are allowed for more demanding performances such as longer filters, input signal precision extension, two-dimensional processing, and increased throughput     

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI

A 300-MHz 16-b fixed-point digital signal processor (DSP) core LSI has been developed for video signal processing. In order to achieve high performance, the DSP core LSI employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design. The DSP core LSI, which was fabricated with 0.5-μm BICMOS and triple-level-metallization technology, has a 3.9 mm×4.6 mm area, and contains about 57K transistors. It consumes 2 W at a 300-MHz clock frequency with a 3.3-V power supply. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively     

A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC

This paper describes a circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for portable audio-visual equipment. Two new circuit techniques, termed pipelined capacitive interpolation and error averaging circuits with capacitor networks, are developed. As a result, very low power dissipation of 30 mW at a low power-supply voltage of 2.5 V is attained at the conversion frequency of 20 MHz. Also, a good DNL of less than ±0.5 LSB and an acceptable signal-to-noise and distortion ratio of 55 dB are obtained for the input frequencies of 1 kHz and 1 MHz, respectively. The ADC is fabricated in 0.8-μm CMOS technology and occupies an area of 2.6×2.5 mm²     

A 4-GHz 8-b ADC system

The system described incorporates silicon bipolar, thick-film hybrid, and CMOS process technologies. A sampler chip providing filtered pulses to four analog-to-digital converter chips on one thick-film hybrid can provide 8 b of resolution and a 2-Gsample/s sampling rate. A novel sampling process called sample and filter is used to reduce the bandwidth requirements of post-sampling circuitry. Two thick-film hybrids with interleaved sample timing were used to obtain a 4-Gsample/s sample rate, 2-GHz bandwidth, and eight effective bits at DC. The goals for system functionality, resolution, bandwidth, and noise were all met with the initial prototypes of the chips and the thick-film hybrid     

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8-μm double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit     

High-speed VLSI arithmetic processor architectures using hybrid number representation

This paper addresses design of high speed architectures for fixed-point, two's-complement, bit-parallel division, square-root, and multiplication operations. These architectures make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We propose newshifted remainder conditioning, andsign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures. Our divider exploits full dynamic range of operands and eliminates the need for on-line or off-line conversion of the result to binary (this is because our nonrestoring division and square-root operators output binary quotient). Furthermore, since the binary input set is a subset of the redundant digit set, no binary-to-redundant number conversion is necessary at the input of the divider and square-root operators. We also present a fast, new conversion scheme for converting radix-2 redundant numbers to two's complement binary numbers, and use this to design a bit-parallel multiplier. This multiplier architecture requires fewer pipelining latches than conventional two's complement multipliers, and reduces the latency of the multiplication operation from (2W–1) to aboutW (whereW is the word-length), when pipelined at the bit-level.This research was supported by the Office of Naval Research under contract number N00014-J-91-1008.     

A 10-b 75-MSPS subranging A/D converter with integrated sample andhold

The design of a fully differential two-step analog-to-digital converter (ADC) is presented. A sample-and-hold (S/H) circuit based on a unity-gain feedback amplifier, flash ADCs driven by differential resistor ladders, and a differential digital-to-analog converter (DAC) combined with the subtractor are described. The chip has been fabricated in a standard high-speed bipolar process and, by extensively utilizing compensation techniques, achieves ±1 LSB integral nonlinearity and low harmonic distortion. A 75 Msample/s conversion rate not yet exceeded even by full-flash 10-b ADCs, has been achieved with a power consumption of 2 W. Due to the S/H circuit, the input bandwidth of 250 MHz; the effective resolution of 9 b at 5 MHz exhibits a gradual decrease over input frequency but still remains above 8 b up to 50 MHz