Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.     

Reliability of Low-Temperature-Processing Hafnium Oxide Gate Dielectrics Prepared by Cost-Effective Nitric Acid Oxidation Technique

In this paper, the physical and electrical characteristics of low-temperature-processing hafnium oxide (HfO₂) films are studied. A simple cost-effective room-temperature process was introduced to prepare high-k HfO₂ dielectrics. A novel technique of direct oxidation of an ultrathin Hf metal by nitric acid, followed by rapid thermal annealing in N₂ is demonstrated. The prepared HfO₂ gate dielectrics show good uniformity, low leakage currents, high breakdown field, and superior reliability under electrical stressing. The long-term ten-year lifetime was also evaluated by a time-dependent-dielectric-breakdown analysis to project the maximum operation voltage of -1.8 V for HfO₂ gate stacks. This low-temperature oxidation technology for preparing high-quality high-k HfO₂ dielectrics is promising for flat-panel-display applications.     

High Voltage Pulsed Power Supply Using IGBT Stacks

High voltage pulsed power supply using IGBT (insulated gate bipolar transistor) stacks and pulse transformer for plasma source ion implantation is proposed. To increase voltage rating, twelve IGBTs are used in series at each IGBT stack and a step-up pulse transformer is utilized. To increase the current rating, the proposed system makes use of synchronized three pulse generator modules composed of diodes, capacitors and IGBT stacks. The proposed pulsed power supply uses semiconductor switches as main switches. Hence, the system is compact, and has semi-infinite lifetime. In addition, it has high flexibility in parameters such as voltage magnitude (10-60 kV), pulse repetition rate (PRR) (10-2000 pps), and pulse width (2-5 muS).     

Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs)

In this paper, an analytical model of the threshold voltage for short-channel symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs) is presented. The three-dimensional (3D) Poisson equation in cylindrical coordinates has been solved with suitable boundary conditions to find the surface potential along the channel length. The inversion charge density \((Q_{inv} )\) has been calculated in the channel region of the device in the subthreshold regime of device operation, using the Boltzmann relationship. Subsequently, the calculated inversion charge density \((Q_{inv} )\) has been equated to a threshold charge density \((Q_{th})\) in order to find the threshold voltage \((V_{th})\) expression. The effect of physical device parameters, including the tube thickness, on the threshold voltage and drain induced barrier lowering (DIBL) of the device has been discussed. The model results have been verified with the simulation data obtained by the device simulation software ATLAS.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

Simulation of thin-TFETs using transition metal dichalcogenides: effect of material parameters,gate dielectric on electrostatic device performance

In recent years, significant of scientific research effort has focused on the investigation of transition metal dichalcogenides (TMDC) and other two-dimensional (2D) materials like graphene or boron nitride. Theoretical investigation on the physical aspects of these materials has revealed a whole new range of exciting applications due to wide tunability in electronic and optoelectronic properties. Besides theoretical exploration, these materials have been successfully implemented in electronic and optoelectronic devices with promising results. In this work, we have investigated the effect of monolayer TMDC materials and monolayer TMDC alloys on the performance of thin tunneling field-effect transistors or thin-TFETs. These are promising electronic devices that can achieve steep switching characteristics. We have used the self-consistent determination of the conduction and valence band levels in the device and a simplified model of interlayer tunneling current reported in recent literature that treats scattering semiclassically and incorporates the energy broadening effect using a Gaussian approximation . We have also explored the effect of gate dielectric material variation, interlayer dielectric variation, top gate metal workfunction on the performance of the device. Our study shows that proper choice of material in the top and bottom layers, optimization of materials used as gate and interlayer dielectric are necessary to extract the full potential of these devices. The electron affinity and bandgap of the TMDCs used in different layers effectively control the threshold voltage and current in the device. As seen from our simulation, interlayer materials with high dielectric constant can degrade subthreshold device performance, increase threshold voltage, whereas lowering interlayer thickness could increase device ‘on’ current at the expense of degraded subthreshold performance.     

Determination of ionization conditions characterizing the breakdown threshold of a point-plane air interval using fuzzy logic

The objective of this paper is to study the discharge phenomenon for a point-plane air interval using an original fuzzy logic system. Firstly, a physical model based on streamer theory with consideration of the space charge fields due to electrons and positive ions is proposed. To test this model we have calculated the breakdown threshold voltage for a point-plane air interval. The same model is used to determine the discharge steps for different configurations as an inference data base. Secondly, using results obtained by the numerical simulation of the previous model, we have introduced the fuzzy logic technique to predict the breakdown threshold voltage of the same configurations used in the numerical model and make estimation on the insulating state of the air interval. From the comparison of obtained results, we can conclude that they are in accordance with the experimental ones obtained for breakdown discharges in different point-plane air gaps collected from the literature. The proposed study using fuzzy logic technique shows a good performance in the analysis of different discharge steps of the air interval.     

A class-AB flipped voltage follower cell with high symmetrical slew rate and high current sourcing/sinking capability

The paper presents a class-AB flipped voltage follower (FVF) cell based on quasi-floating gate and bulk-driven techniques. The quasi-floating gate technique is used to increase the current sinking capability, whereas the bulk-driven technique is used to enhance the current sourcing capability by reducing the threshold voltage. Using these two techniques, the proposed class- AB FVF cell offers high current sinking and sourcing capabilities. Also, it provides high symmetrical slew rate without any additional circuitry. The physical layout of the proposed class- AB FVF cell has been designed in Cadence Virtuoso Layout XL editor using BSIM3v3 180-nm CMOS technology, and post-layout simulation results have been presented to validate its performance. The corner analysis of the proposed class- AB FVF cell has also been performed with temperature and supply voltage as design variables to show its performance under extreme conditions.     

The Sparking Characteristics of Needle-To-Plane Coronas

The sparking voltage (Vs) and maximum presparking corona current (Imax) of needle-to-plane coronas have been measured as independent functions of polarity, tip radius (r), and needle-to-plane spacing (S). For a negative needle, Vs and Imax increase with S but are independent of r. For positive polarity, Vs and Imax increase with both S and r. Thus to increase the corona current while avoiding a spark, one should increase the spacing and voltage. At large spacings, Imax is appreciably greater for negative polarity than for positive. Analysis of the data reveals that for negative polarity the maximum presparking current may be written in the approximate form Imax?Vs(Vs-VO)S-2 where VO is the corona threshold voltage. This is an extrapolation of a relationship previously obtained for Trichel pulse corona. The analysis shows that the transition from negative corona to sparking occurs when the linear space charge density in the gap reaches a critical value Qs/S ?10-10 coul/mm, where Qs is the total space charge in the gap just before sparking occurs. It is shown that this condition amounts to spatial overlap of the multiple ion clouds in the gap, thereby creating a continuous ionized channel between the electrodes.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

Mobility in high-k/metal-gate Ultra-Thin Body and Box Fully Depleted SOI devices has been extensively investigated by means of multi-scale simulations and experimental data. Split-CV mobility measurements have been performed for various Interfacial Layer Equivalent Oxide Thickness allowing an investigation of the physical mechanisms responsible for the mobility degradation at high-k/Interfacial layer interface. The impact of the back bias on transport properties is investigated and mobility enhancement in the reverse regime (back gate inversion) is studied. A multi-scale simulation strategy is ranging from quantum Non-equilibrium Green’s Functions to semi-classical Kubo Greenwood approach. These advanced solvers made possible a throughout calibration of empirical TCAD mobility models.     

Searching for short-term techniques for the inference of electricalthreshold of PET. DC conductivity measurements

A possible way for the detection of electrical threshold in dielectric polymers is illustrated in this paper. On the basis of the consideration that the lowest threshold level for electrical aging is related to build up of steady space charge, high-field current measurements performed at different voltage and temperature values, seeking space charge limited current conditions, can provide estimations of electric field at threshold. This approach is applied to PET films under dc voltage. The values of electrical threshold thus obtained are compared with those derived from conventional accelerated life testing, showing that there is good correspondence of values at the lowest temperature of the test range, while deviation between estimates increases with temperature     

调压型电荷泵

现今许多电子产品用电池作为电源，但是电池并不能稳定且持续保持固定的电压。为了提供系统稳定并且高于电源的电压，电荷泵与电压的调节是相当重要的。藉由带隙参考电压(bandgap reference)，调节电荷泵提供稳定的电压并不困难。但是在商业产品的制造上，带隙参考电压电路的制造却会增加生产上的复杂度。为了克服这个问题，本文将讨论如何不使用带隙参考电压而能调节输出电压的电荷泵。本设计的电荷泵使用交互连结式(cross-coupled type)的电路架构。并且利用一个弛张式震荡器来提供电荷泵驱动的频率。为了使用脉冲跨越模式(pulse-skip mode)来调节输出电压，利用修正弛张式震荡器内部的操作电流来控制频率。晶体管的门限电压(threshold voltage)被用来取代参考电压值，并且利用一个P型晶体管去检测输出电压的量值，若电压值高过设定的电压，则P型晶体管将导通，并且提供信号将弛张式震荡器关闭，此时电荷泵将停止升压。     

Electron transport properties of electrically doped guanine nano-sheet based bio-Zener diode: a first principle paradigm

The quantum ballistic transmission properties of an electrically-doped guanine-nanosheet-based bio-Zener diode are investigated using density functional theory and nonequilibrium Green’s function-based first-principles calculations. The bio-Zener diode is gate-bias modulated, and its various quantum-electronic properties, for example, the V–I characteristic, the transmission spectra, and the device density of states, depend on both the electrical doping concentration and on the applied gate bias voltage. The junctionless highly doped bio-Zener diode shows high levels of reverse-bias current which is dominated by majority charge carriers. It is also found that, due to the presence of a wide bandgap and the backscattering effect, the forward-bias current is highly suppressed. The quantum simulation results confirm a strong reverse gate-bias-modulated biased current–voltage response as well as a charge transport phenomenon through the effective device region. The bio-Zener diode exhibits a specific reverse breakdown that can be varied from ?0.78 to ?3.2 V without affecting the forward current–voltage characteristic. The current findings are obtained by including the coherent tunneling and incoherent hopping processes with a minimal Hamiltonian model approach.

     

“Atomistic”, Quantum and Ballistic Effects in Nanoscale MOSFETs

In this paper we describe the effects of quantum confinement and ballistic transport in the channel on the dispersion of threshold voltage due to the discrete distribution of dopants. To this aim, a recently developed 3D Poisson-Schrödinger solver is used, along with a 2D solver of ballistic transport. The Schrödinger equation is solved with density functional theory, in the local density approximation. Results on statistically meaningful ensembles of devices show that both ballistic transport and quantum confinement lead to an increase of threshold voltage dispersion.     

气压湿度对负直流电晕特性影响的研究

为得到负直流电晕特性随着气压湿度的变化规律,建立了考虑气压湿度影响的负直流电晕起始电压的物理模型,利用模拟电荷法和计算表面光电子数目的方法求解了负直流电晕起始电压。在人工气候罐中,利用棒–板电极,测量了不同气压湿度下的负直流电晕起始电压和电晕电流。计算和试验结果表明:电晕起始电压随气压下降、湿度升高而减小,主要原因分别是有效电离系数增大导致的电离区域的扩大和高场强区域内碰撞电离能力的增强。当直流电压和电晕起始电压的比值一定时,电晕电流随气压下降、湿度升高而减小;当直流电压一定时,电晕电流随气压降低而增大,随湿度升高而减小。电晕电流和直流电压、电晕起始电压关系式中的系数C随湿度增大的不同变化趋势和正负离子与水分子结合状态的差异有关。     

大功率电机直接起动的逆变器控制模式切换策略

在冲击性负荷下(如短路故障)要保证逆变器可靠地运行,采用两种控制模式:正常情况下,逆变器输出恒定电压,工作于电压控制模式;异常情况下(如短路、冲击性负载),逆变器输出电流恒定,工作于电流控制模式。两种控制模式的切换成为逆变器可靠运行的关键技术之一。常用的切换策略:故障的负载电流值大于电流阈值和故障消除的负载电压恢复到额定电压进行模式切换。但是,为解决冲击性负载下可靠地保护,希望进入电流控制模式的电流阈值较低,而在特定的负载下安全地直接起动大容量电机(电机的起动电流一般是额定电流的几倍甚至上十倍),则希望电流阈值较高。针对二者矛盾,文中利用大功率电机起动与故障工况的差异,再引入电压阈值作为判断条件解决了电机起动误入电流控制模式的问题,两台400kV.A、50Hz的样机实验验证了该策略的有效性。     

Modeling and comparative analysis of DC characteristics of AlGaN/GaN HEMT and MOSHEMT devices

In this paper, a charge control model is developed for AlGaN/GaN High Electron Mobility Transistor (HEMT) and Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) by considering the triangular potential well in the two‐dimensional electron gas (2DEG) and simulated with matlab . The obtained results from the developed model are compared with the experimental data for drain current, transconductance, gate capacitance and threshold voltage of both devices. The physics‐based models for 2DEG charge density, threshold voltage and gate capacitance have been developed. By using these developed models, the drain current for both linear and saturation modes is derived. The predicted threshold voltage with the variation of barrier thickness has been plotted. A positive threshold voltage can be obtained by decreasing the barrier thickness that builds up the foundation for enhancement mode MOSHEMTs. The predicted C‐V, I_d‐V_gs, I_d‐V_ds and transconductance characteristics show an excellent agreement with the experimental results from the literature and hence validate the developed model. The results clearly establish the potential of using AlGaN/GaN MOSHEMT approach for high power microwave and switching applications. Copyright © 2015 John Wiley & Sons, Ltd.     

Stacked dual-oxide MOS energy band diagram visual representation program (IRW student paper)

Energy band diagrams for MOS devices are essential for understanding device performance and reliability. Introduction of high-k gate stacks with a silicon dioxide (SiO/sub 2/) interfacial layer requires an even greater understanding of the energy band behavior. A program that quickly determines the band diagrams based on a simple analytical model was created. It is used to explore the behavior of various oxide stacks with the ability to easily vary important parameters like oxide material, electron affinity, bandgap, dielectric constant, and thickness. The usefulness of this program to predict potential reliability issues is also demonstrated.