A 45-channel 100 GHz AWG based on Si nanowire waveguides

A 45-channel 100 GHz arrayed waveguide grating (AWG) based on Si nanowire waveguides is designed, simulated and fabricated. Transfer function method is used in the spectrum simulation. The simulated results show that the central wavelength and channel spacing are 1 562.1 nm and 0.8 nm, respectively, which are in accord with the designed values, and the crosstalk is about ?23 dB. The device is fabricated on silicon-on-insulator (SOI) substrate by deep ultraviolet lithography (DUV) and inductively coupled plasma (ICP) etching technologies. The 45-channel 100 GHz AWG exhibits insertion loss of 6.5 dB and crosstalk of ?8 dB. This work has been supported by the National High Technology Research and Development Program of China (No.2015AA016902), and the National Natural Science Foundation of China (Nos.61435013 and 61405188). E-mail:zhangjiashun@semi.ac.cn      

基于绝缘体上硅材料的25通道200 GHz的阵列波导光栅

报道了基于绝缘体上硅材料的25通道、信道间隔200 GHz的阵列波导光栅, 分别优化了输入波导/输出波导/阵列波导间的最小间距 (Δxi/Δxo/d) , 及其自由传播区和阵列波导之间边界结构 (W2/L2/L3) .实验结果表明, 该阵列波导光栅的插入损耗为5～7 dB, 串扰为13～15 dB, 该阵列波导光栅的性能得到有效提升.同时也提出了减小插损与串扰的进一步优化方案.     

基于硅纳米线波导的16通道200GHz阵列波导光栅

设计了基于硅纳米线波导的16通道,通道间隔为200GHz的阵列波导光栅(AWG)。传输函数法模拟了器件传输谱,结果表明器件的通道间隔为1.6nm,通道间串扰为31dB。器件利用SOI材料,由193nm深紫外光刻工艺制备。光谱测试结果分析表明,通道串扰为5-8dB,中心通道损耗2.2dB,自由光谱区长度24.7nm,平均信道间隔1.475nm。详细分析了器件谱线畸变的原因。     

16 channel 200 GHz arrayed waveguide grating based on Si nanowire waveguides

A 16 channel arrayed waveguide grating demultiplexer with 200 GHz channel spacing based on Si nanowire waveguides is designed.The transmission spectra response simulated by transmission function method shows that the device has channel spacing of 1.6 nm and crosstalk of 31 dB.The device is fabricated by 193 nm deep UV lithography in silicon-on-substrate.The demultiplexing characteristics are observed with crosstalk of 5-8 dB,central channel’s insertion loss of 2.2 dB,free spectral range of 24.7 nm and average channel spacing of 1.475 nm.The cause of the spectral distortion is analyzed specifically.     

Design and fabrication of ultra-small overlapped AWG demultiplexer based on /spl alpha/-Si nanowire waveguides

A novel layout for an ultra-compact arrayed-waveguide grating (AWG) demultiplexer is presented. The present layout has two overlapped free propagation regions, and is more compact than a conventional layout. Using /spl alpha/Si-on-SiO/sub 2/ nanowire waveguides, an ultra-small 4/spl times/4 AWG (about 40/spl times/50 /spl mu/m/sup 2/) with channel spacing of 11 nm is fabricated and characterised.     

基于Si纳米线AWG的超紧凑单纤三向滤波器设计

采用绝缘层上Si(SOI)纳米线阵列波导光栅(AWG)结构设计了超紧凑光纤到户(FTTH)单纤三向滤波器。二维时域有限差分(2D-FDTD)模拟输出光场表明,3个波长光信号输出光场清晰,实现了1490 nm和1550nm下行波长的解复用和1310 nm波长的上传复用功能;进一步的输出功率模拟表明,当各波长信号输入功率为1 mW时,1490 nm端口输出功率为0.49 mW,1550 nm端口输出功率为0.49 mW,1310 nm上传信号功率为0.55 mW,相应的插入损耗分别约为-3.1、-3.1和-2.6 dB。各端口的串扰光功率可被抑制到-25.2 dBm以下,相应的串扰小于-22.6 dB。采用电子束(EB)光刻结合诱导耦合等离子干法(ICP-RIE)刻蚀,制备出了Si纳米线单纤三向滤波器,经红外CCD成像观察到器件具有3个波长的分波功能。     

Design and fabrication of ultrasmall arrayed waveguide grating multiplexers based on Si nanowire waveguides

In the past decades, integrated optical devices based on planar lightwave circuits (PLCs) have been developed rap- idly and used in various areas, such as optical communications, optical sensing and, etc. Because of their excellent performances and the feasibility for massive productions, PLC-based integrated optical devices may take the place of discrete devices more and more in the future. In order to satisfy the increasing demands of the optical net- works with a large capacity and high s…     

400-channel arrayed-waveguide grating with 25 GHz spacing using1.5%-Δ waveguides on 6-inch Si wafer

A large-scale arrayed-waveguide grating with a 400-channel and 25 GHz spacing using 1.5%-Δ silica-based waveguides on a 6-inch Si wafer has been realised. Good demultiplexing properties have been obtained over the full Cand L-band range with an on-chip loss of 3.8 to 6.4 dB and a far-end crosstalk of -30 dB     

128-channel polarization-insensitive frequency-selection-switchusing high-silica waveguides on Si

A 128-channel polarization-insensitive frequency-selection-switch (FS-SW) with 10-GHz frequency spacing is discussed. The FS-SW was fabricated on Si using low-loss GeO₂-doped high-silica waveguides, and its frequency-insensitive operation was attained by the laser trimming adjustment of a-Si film which controls waveguide birefringence. The fiber-to-fiber loss of the transmitted channel was 6.7 dB in the pigtailed FS-SW and the total crosstalk level was less than -13 dB. By using this FS-SW, a 100-channel optical frequency division multiplexing (FDM) transmission-distribution experiment at 622 M b/s over a 50-km fiber length was achieved     

8通道-1.6nm Si纳米线阵列波导光栅的设计与制作

设计了基于绝缘层上硅(SOI)材料的8通道Si纳米线阵列波导光栅(AWG),器件的通道间隔为1.6nm,面积为420μm×130μm。利用传输函数法模拟了器件传输谱,结果表明,器件的通道间隔为1.6nm,通道间串扰为17dB。给出了结合电子束光刻(EBL)和感应耦合等离子(ICP)刻蚀技术制备器件的详细流程。光谱测试结果分析表明,器件通道间隔为1.3～1.6nm,通道串扰为3dB,中心通道损耗为11.6dB。     

Design of ultra-compact wavelength splitter based on lithium niobate nanowire optical waveguides

A wavelength splitter with ultra-compact and simple structure is proposed and analyzed by using both plane wave expansion(PWE) method and finite difference time domain(FDTD) method.The device is based on directional coupling between two parallel lithium niobate(LiNbO3,LN) nanowire optical waveguides.The wavelength splitter with a coupling region length of 5 μm can separate 1.31μm and 1.55 μm wavelengths for corresponding outputs with transmittance higher than 97%.     

50/100GHz AWG型光学梳状滤波器的设计与制备

以Si基SiO2平面光波导为基础,设计并制备了50/100GHz AWG型光学梳状滤波器．制备得到的AWG型光学梳状滤波器可以覆盖1520～1585nm的波长范围,共有160个信道．功率输出不均匀度＜0.5dB,插入损耗＜8dB,相邻通道的串扰＞13dB,在距离中心频率最远的信道,输出频率偏离ITU标准15GHz．分析了影响器件串扰和信道频率偏移的原因,并提出了相应的解决办法．     

50/100GHz AWG型光学梳状滤波器的设计与制备

以Si基SiO2平面光波导为基础,设计并制备了50/100GHz AWG型光学梳状滤波器.制备得到的AWG型光学梳状滤波器可以覆盖1520～1585nm的波长范围,共有160个信道.功率输出不均匀度＜0.5dB,插入损耗＜8dB,相邻通道的串扰＞13dB,在距离中心频率最远的信道,输出频率偏离ITU标准15GHz.分析了影响器件串扰和信道频率偏移的原因,并提出了相应的解决办法.     

Design and fabrication of compact etched diffraction grating demultiplexers based on a-Si nanowire technology

alpha-silicon nanowire waveguides and related techniques are studied. An ultra-compact etched diffraction grating demultiplexer with 10 nm spacing is fabricated and characterised. The dimension of the device is around half a millimetre, which is one to two orders of magnitude smaller than conventional silica based devices.     

基于CPLD和单片机的任意波形发生器设计

本文介绍了一种新型任意波形发生器(AWG)的设计方法.该方法利用MATLAB的仿真功能,采用复杂可编程逻辑器件(CPLD)和单片机控制相结合,得到所需的信号波形.     

Design and fabrication of silicon photonic crystal optical waveguides

We have designed and fabricated waveguides that incorporate two-dimensional (2-D) photonic crystal geometry for lateral confinement of light, and total internal reflection for vertical confinement. Both square and triangular photonic crystal lattices were analyzed. A three-dimensional (3-D) finite-difference time-domain (FDTD) analysis was used to find design parameters of the photonic crystal and to calculate dispersion relations for the guided modes in the waveguide structure. We have developed a new fabrication technique to define these waveguides into silicon-on-insulator material. The waveguides are suspended in air in order to improve confinement in the vertical direction and symmetry properties of the structure. High-resolution fabrication allowed us to include different types of bends and optical cavities within the waveguides.     

基于硅线波导的AWG的设计及仿真

基于以SOI材料为衬底的Si线波导,设计了一种光缆线路自动监测系统中的1×2阵列波导光栅波分复用器,对应两波长分别为1550nm、1625nm,其尺寸仅为117×217 μm2,远小于目前技术较成熟的硅基SiO2 AWG的尺寸.对应两波长处的插入损耗分别为-1.157dB、-1.227dB,串扰分别为35dB、43dB.     

标准CMOS工艺栅控Si-LED设计与制备

采用新加坡半导体制备有限公司的0.35um EEPROM双栅标准CMOS工艺设计和制备了U型Si-LED发光器件。器件结构采用P+-N+-P+-P+-P+-N+-P+-P+-P+-N+-P+叉指结构形成U型器件,外部的两个P+区为保护环,在相邻的内部两个P+区之间使用多晶硅作为栅极来调控LED的正偏发光。使用奥林巴斯IC显示镜测得了硅LED实际器件的显微图形,并对器件进行了电学的正反向I-V特性测量。器件在室温下正向偏置,在100～140mA电流下对器件进行了光功率的检测,发光峰值在1089nm处。结果表明,器件发光功率随着栅控电压偏置电流的增加而增加。     

工艺误差对AWG串扰特性的影响

分析了阵列波导光栅器件的制作过程中引入的各种工艺误差。对波导尺寸误差、折射率误差以及长度误差进行了等效,并计算了位相误差和振幅误差的方差。最后分析了位相误差和振幅误差对阵列波导光栅的频谱特性尤其是相邻通道间的串扰特性的影响。     

DESIGN AND FABRICATION OF Si/SiGe PMOSFETs

Based on theoretical analysis and computer-aided simulation, optimized design prin-ciples for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials, determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage.In the light of these principles, a SiGe PMOSFET is designed and fabricated successfully.Measurement indicates that the SiGe PMOSFET‘s(L=2μ同洒45 mS/mm(300K) and 92 mS/mm(77K) ,while that is 33mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.