RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time     

微型光机电系统及其制作

微型光机电系统 (MOEMS)是将微光学、微电子和微机械系统结合发展出一种新型、宽广的应用领域 ,从早期的分立光学元件与电子电路向独立完整的光学系统发展。阐述了实现MOEMS的 2种技术手段 :光波导和微型光学平台的原理、制作工艺和关键技术 ,在此基础上概要介绍了几种典型的MOEMS系统。最后对其的发展作了展望。     

基于衍射/反射光束整形系统的高密度泵浦源

利用二元光学元件微型化和对波面进行任意整形的特点,将二元光学衍射器件用于高功率激光二极管阵列光束的快、慢轴准直,并结合空心导管设计一种衍射/反射混合型光束整形系统,用于实现高密度、高均匀性LD泵浦源.应用时域有限差分法(FDTD)的严格矢量分析表明:所设计的二元光学准直器性能优良,准直后光束发散角在误差范围内接近衍射极限,慢轴方向衍射效率为82.21%,快轴方向为75.76%.模拟设计的结果表明:采用这种衍射/反射光束整形技术的高密度泵浦源能获得高功率密度和高均匀性的抽运光束,在空心导管出射端面附近光强起伏RMS<1%,并且在光束的准直性能和系统紧凑性方面优于传统整形方法.     

Guided-wave planar optical interconnects using highly multiplexedpolymer waveguide holograms

An intraplanar interconnection scheme using substrate guided modes in conjunction with a highly multiplexed waveguide volume hologram is proposed. Acoustooptically addressed 1-to-50 passive and 1-to-2-to-100 reconfigurable interconnections with a fan-out diffraction efficiency of 55% at 514-nm wavelength are demonstrated. A coordinate transformation converts the 3-D diffraction problem into a 2-D one, which significantly simplifies the theoretical calculation. Intraplane massive fan-out optical interconnection using substrate guided mode provides both collinear and coplanar fan-out capability for data and clock signals. Colinearity of signal distribution allows the 2-D input signal array to be processes. The laminated waveguide device containing a highly multiplexed dichromated gelatin (DCG) hologram has been evaluated     

用于惯性约束聚变驱动器的色分离光栅-光束采样光栅集成元件的制作

针对惯性约束聚变(ICF)驱动系统特别是其终端光学系统对元件数和元件厚度的限制要求,利用衍射光学元件(DOE)易于集成的优点,提出一种在石英基片的两面分别曝光制作色分离光栅(CSG)和光束采样光栅(BSG)的新方法,仅需一个石英片即可同时实现谐波分离和光束采样的功能.分别采用光学制版和电子束直写的方法制作了色分离光栅和光束采样光栅的掩模,并利用离子束刻蚀的方法加工了色分离光栅-光束采样光栅集成元件.结果表明,此集成元件的三倍频光能量利用率、色分离度以及采样效率等参数均与三倍频光通过色分离光栅、光束采样光栅分离元件时得到的结果相吻合,达到了惯性约束聚变激光驱动器终端光学系统的基本技术指标要求.     

Time-transfer performance in burst-mode communication systems

This paper studies the performance of the clock transfer scheme for burst-mode communication systems for which data are received during short, equally spaced intervals. Its main focus is on satellite-based time-division multiple-access (TDMA) communication systems with data regeneration and switching onboard the satellite, although the results apply to other TDMA systems as well. The system reference clock is generated onboard from an incoming, very stable ground source, based on a burst-mode demodulator that extracts the clock from a discontinuous modulated carrier due to the bursty nature of TDMA signals. If good enough, this onboard regenerated clock avoids the use of bulky and expensive clocks in the satellite payload and can act as the master clock of the TDMA system     

激光直写制备衍射光学元件的研究及应用

衍射光学元件作为一种典型的微光学元件,其体积小、质量轻、设计自由度多、成像质量良好,在光学成像、光学数据存储、激光技术、生物医学等领域具有广阔的应用前景。随着现代光学系统的不断发展,对衍射光学元件的加工效率和制备精度提出了更高的要求。激光直写技术凭借加工精度高、工艺简单、灵活性好等优势,成为制备高精密仪器中关键光学元件所必需的一种加工方式。针对不同的加工需求,开发了多种激光直写系统,并在应用过程中不断地改进升级。另外,突破衍射极限的飞秒激光微纳结构制造技术,能够获得更高的加工精度和更好的分辨率,为微光学元件的制备提供了新的方法。首先介绍了激光直写技术的特点;其次综述了衍射光学元件直写加工技术的研究进展,包括直写技术的影响因素、激光直写系统和多光束加工技术;接着介绍了衍射光学元件的典型应用,如红外成像、色差校正、光束整形、图像显示;最后,对激光直写技术制备衍射光学元件存在的问题和未来发展趋势做出了总结。     

跨时钟域信号的几种同步方法研究

为使跨时钟域信号能够被目标时钟正确采集,提出并总结了几种同步方法,详尽论述了这些方法所涉及的存储器计算和synthesis设置。跨时钟域信号的同步方法应根据源时钟与目标时钟的相位关系、该信号的时间宽度和多个跨时钟域信号之间的时序关系来选择。如果两时钟有确定的相位关系,可由目标时钟直接采集跨时钟域信号,且在synthesis中应设此两时钟为同步关系;否则,需要借助FIFO(First in,First out),在synthesis时,此两时钟必须设为false path关系。跨时钟域信号的宽度至少应为目标时钟周期的两倍。对于彼此有确定时序关系的多个跨时钟域信号,在同步前应使其保持足够距离。所述方法在CMOS(Complementary Metal Oxide Semiconductor)图像传感器的设计中被实际应用。经仿真和芯片的系统验证,该图像传感器可以正确完成信号在各时钟间的同步,并以60帧/s的速率正确输出分辨率为1 280×720的数据。     

Parallel architectures for digital optical cellular imageprocessing

A parallel digital optical cellular image processor (DOCIP) functionally comprises an array of identical I-bit processing elements or cells, a fixed interconnection network, and a control unit. Four interconnection network topologies are described, and include two variants of a mesh-connected array and two variants of a cellular hypercube network. The instruction sets of these single-instruction multiple-data (SIMD) machines are based on a mathematical morphological theory, binary image algebra (BIA), which provide an inherently parallel programming structure for their control. Physically, a DOCIP architecture uses a holographic optical element in a 3D free-space optical system to implement off-chip interconnections, and an optoelectronic spatial light modulator to implement a 2D array of nonlinear processing elements and (optionally) local on-chip interconnections. Two examples are given. The first, an experimental implementation of a single 54-gate cell of the DOCIP, uses an optically recorded hologram for within-cell optical interconnections, and a spatial light modulator for a 2D array of optically accessible gates. The second, a design for an efficient and more manufacturable architecture, uses a computer-generated diffractive optical element for cell-to-cell interconnections, and a 20 smart-pixel array of DOCIP cells, each cell having electronic logic and optical input/output     

底发射VCSEL片上点阵结构光投影装置设计

为解决现有点阵结构光投影装置中准直透镜会导致较强的零级衍射而造成投影点阵光强分布不均匀的问题,提出了一种基于底发射垂直腔面发射激光器的片上点阵光投影装置结构,并给出了衍射光学元件设计思路。首先对目标光场进行光强调整和坐标变换,在无准直透镜情况下利用基于瑞利-索末菲衍射积分的Gerchberg-Saxton改进算法获得片上衍射光学元件的相位分布,并最终对该点阵投影装置的投影效果进行评估。结果表明:在衍射光学元件设计过程中采用高斯光束作为光源时,该结构能更好地抑制零级衍射,获得光强分布更加均匀的投影点阵。此外,该结构不仅可省去透镜的安装,减小投影装置尺寸,还可通过流片工艺实现光源和衍射光学元件一体化集成。     

Optical interconnections for VLSI systems

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The origins of the communication crisis are discussed. Those aspects of electrooptic technology that are applicable to the generation, routing, and detection of light at the level of chips and boards are reviewed. Algorithmic implications of interconnections are discussed, with emphasis on the definition of a hierarchy of interconnection problems from the signal-processing area having an increasing level of complexity. One potential application of optical interconnections is to the problem of clock distribution, for which a single signal must be routed to many parts of a chip or board. More complex is the problem of supplying data interconnections via optical technology. Areas in need of future research are identified.     

A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology

This paper describes a full-rate-clock 4:1 multiplexer (MUX) in a 0.13-/spl mu/m InP-based HEMT technology for 40-Gb/s and above optical fiber link systems. To reduce output jitter, the serialized data are retimed at the final stage by a retimer, a D-type flip-flop, which has a symmetric layout with an optimized spacing to the ground that minimizes coupling capacitances. A phase adjuster, composed of an exclusive OR and a delay switch, uses external control signals to change each phase of the serialized data and clock entering the retimer and gives a correct timing for the clock to drive the retimer. A clock distributor with a simple wired splitter divides the clock into two clocks with high gain and low current. The MUX integrates 1355 HEMTs formed using electron beam lithography. A chip mounted in a test module operated at up to 47 Gb/s with a power consumption of 7.9 W for a single supply voltage of -5.2 V.     

基于F-P滤波器的多波长时钟提取

提出一种简单的全光单一链路的多波长时钟同时提取方案。利用Fabry-Perot(F-P)滤波器对波分复用(WDM)系统中多波长的归零(RZ)码信号进行时钟提取,滤波器后面接半导体光放大器(SOA)对F-P滤波器提取出的时钟进行整形处理,通过实验证实了用F-P滤波器对两路不同波长的10 Gbps信号时钟提取的可行性以及同一SOA同时处理双波长时钟的能力,两路提取时钟的单边带相位噪声分别达到-82.815和-83.072dBc/Hz@10 kHz。     

Architectural considerations involved in the design of an optical digital computer

Communication problems such as interconnection bandwidth, clock skew, and connectivity restrict computational throughput. Bandwidth and clock skew problems limit the speed and add to the design complexity. Constrained connectivity forces a significant portion of the speed of a processor to be used to compensate for the limited number of interconnections. Philosophically, the large bandwidth, innate parallelism, and noninterfering propagation of optics offer mechanisms for overcoming these communication problems. The difficulty in exploiting these capabilities has been the absence of suitable optical logic and memory devices. Technologically, optical bistability and other advances in electrooptics now offer the possibility of cascadable optical logic elements with speed and power dissipation comparable with electronics. Architecturally, a parallel pipelined structure can be used to simplify the optical memory requirements as well as exploit the communication capabilities of optics.     

二元光学法在微透镜制作中的应用

对二元光学的产生和发展作了介绍,并阐述了二元光学元件之一的微透镜(microlenses)的设计、制作和测试方法以及它们的主要应用。微透镜的设计是基于已成熟的标量衍射理论;而其制作过程包括:计算机设计波面相位、产生掩模版、光刻或离子(束)蚀刻以及复制产生微透镜,其关键技术蚀刻方法有等离子蚀刻技术和反应离子蚀刻RIE(Reactive Ion Etching)技术;微透镜的测试主要包括衍射效率(diffractive efficiency)和点扩散函数(PSF)的测试,有直接法和间接法两种测试方法。微透镜可以微型化与阵列化,并且可以同微电子器件一起集成化,具有广泛的应用前景。     

High-density digital free-space photonic switches using micro-beam optical interconnections

We describe a compact free-space photonic-switching module that uses micro-beam optical interconnections based on stacked planar optics and exciton absorption reflection switch (EARS) arrays. The switching module has two-dimensional fiber array pigtails and a two-stage, 16-input, 16-output structure (four sets of 4/spl times/4 switches). The microbeam optical interconnections can provide a compact switching module (approximately 30/spl times/90/spl times/22 mm [60 cc]). A relay lens array inserted between stages eliminates beam spreading in the switch and decreases the coupling loss and crosstalk of interconnections. Two-stage switching at a data transmission rate of 4 Mbit/s is demonstrated.     

微透镜及其应用简介

对二元光学的产生和发展作了介绍，并阐述了二元光学元件之一的微透镜（microlenses）的设计、制作和测试方法以及它们的主要应用。微透镜的设计是基于已成熟的标量衍射理论；而其制作过程包括：计算机设计波面相位、产生掩膜板、光刻或离子（束）蚀刻以及复制产生微透镜，其关键技术蚀刻方法有等离子蚀刻技术和反应离子蚀刻RIE（Reactive Ion Etching）技术；微透镜的测试主要包括衍射效率（diffractive efficiency）和点扩散函数（PSF）的测试，有直接法和间接法两种测试方法。微透镜可以微型化与阵列化，并且可以同微电子器件一起集成化，具有广泛的应用前景。     

Comparing lock-in ranges and transient responses of second- and third-order phase-locked loops in master–slave clock distribution networks

The distribution of clock signals throughout the nodes of a network is essential for several applications in control and communication with the phase-locked loop (PLL) being the component for electronic synchronization process. In systems with master–slave (MS) strategies, the PLLs are the slave nodes responsible for providing reliable clocks in all nodes of the network. As PLLs have nonlinear phase detection, double-frequency terms appear and filtering becomes necessary. Imperfections in filtering process cause oscillations around the synchronous state worsening the performance of the clock distribution process. The behavior of one-way master–slave (OWMS) clock distribution networks is studied and performances of first- and second-order filter processes are compared, concerning lock-in ranges and responses to perturbations of the synchronous state.     

Fiber-optic digital video multiplexing using optical CDMA

The use of laser pulsing in the form of code-division multiple access (CDMA) to multiplex a set of digital video signals over a fiber network is proposed. The laser pulsing is used to generate unique code sequence addresses which identify each source, and the video data are modulated on these sequences. Digital encoding using pulse position modulation (PPM) is proposed, having advantages that permit efficient integration of optical and electronic processing. Data recovery is achieved by optical correlation for sequence recognition, followed by standard electronic PPM decoding. The relation between key system parameters of the encoding, decoding, and optics is derived, and indicates that compressed video rates between 5 and 20 Mb/s/channel, with 25-50 channels, is possible with relatively standard hardware. Experimental breadboard results being carried out at USC on this system indicate the feasibility of the CDMA concept for fiber multiplexing     

伪卫星时钟同步方法的研究

提出了一种全新的利用光网络实现伪卫星时钟同步的方法,并设计出了一套基于光网络的高可靠性、高精度的时钟同步系统,实现了不同时钟之间的精密时间同步,同步精度优于1 ns.