Physical timing modeling for bipolar VLSI

An approach for the analytical timing modeling of bipolar VLSI circuits that is based on average branch current analysis and the parametric correction scheme is presented. The combination of these techniques permits complex delay-sensitive effects of bipolar digital circuits to be incorporated in the derivation of the bipolar delay models. The delay functions of two basic bipolar subcircuit configurations (the series-gated structure and the emitter follower) are derived using the proposed techniques. It is shown that accurate timing information for the high-speed bipolar digital circuit, such as ECL, CML, and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The delay estimates obtained with these timing models have been shown to be accurate typically within 10% of SPICE estimates. Applications include switch-level timing simulation, timing analysis and verification cell optimization, and technology mapping     

Advances in bipolar VLSI

Bipolar IC processes are reviewed, and the impact of BiCMOS technology on bipolar VLSI is discussed. The discussion covers standard emitter-coupled-logic (ECL) circuit configuration, on-chip line driving, output circuitry, series gating, ECL versus CML (current-mode logic), differential logic, noise margins, interconnect capacitance, bipolar VLSI transistor design and scaling, and processes for ECL VLSI     

Characterization of CMOS devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Optimum performance (minimum figure of merit FM = tpdPd) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, CL= 22 fF) with an electrical channel length L = 0.75 µm, channel width W = 5.0 µm, and oxide thickness Xo= 450 Å with VDD= 3.0 V, to yield tpd= 400 ps and Pd= 250 µW (tpdPd= 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for tpdand Pd. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for tpddescribes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchial modeling approach to characterize minicells for VLSI.     

A compact model for multiterminal bipolar devices used in smartpower applications

Complex technologies merging low-voltage bipolar devices and vertical current-flow power transistor allow more smart functions at low chip cost but pose problems during the design phase because there is no way to predict the influence of the high-voltage transistor over the control components by using standard bipolar junction transistor (BJT) models. In fact the large inductive load usually present in high-voltage power transistors applications forces both negative substrate voltage and spurious currents that can induce positive feedback among parasitic devices, downgrading the performance of a single device and so of the whole circuit. In this work we introduce a model for the five-terminal bipolar devices used in smart power applications. The model accounts for all main static and dynamic parasitic effects and gives results in very good agreement with experimental data on both simple devices and complex integrated circuits currently implemented in commercial products for microprocessor based engine management systems (EMS's)     

Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion

This paper reports a closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted (FD) SOI NMOS devices with lightly-doped drain (LDD) structure. As verified by the two-dimensional (2-D) simulation results, the analytical drain current model considering energy transport and self-heating provides an accurate prediction of the drain current behavior of the 0.25-/spl mu/m FD SOI NMOS device with and without an LDD structure. From the analytical model, with the LDD structure, the device has a smaller effective electron mobility at a low drain voltage, where lattice temperature is dominant, and a higher effective mobility at a high drain voltage, where electron temperature dominates, as compared to the non-LDD device.     

Self-aligned bipolar transistors for high-performance and low-power-delay VLSI

An n-p-n bipolar transistor structure with the emitter region self-aligned to the polysilicon base contact is described. The self-alignment results in an emitter-to-base contact separation less than 0.4 µm and a collector-to-emitter area ratio about 3:1 for a two-sided base contact. This ratio can be less than 2:1 for a base contacted only on one side. The vertical doping profile can be optimized independently for high-performance and/or high-density and low-power-delay circuit applications. The technology, using recessed oxide isolation, was evaluated using 13-stage nonthreshold logic (NTL) and 11-stage merged-transition logic (MTL) ring-oscillator circuits designed with 2.5 µm design rules. For transistors with 200-nm emitter junction depth the common-emitter current gain for polysilicon emitter contact is typically 2-4 times that for Pd2Si emitter contact. There is no observable circuit performance degradation attributable to the polysilicon emitter contact. Typical observed per-stage delays were 190 ps at 1.3 mW and 120 ps at 2.3 mW for the NTL (FI = FO = 1) circuits and 1.3 ns at 0.15 mA for the MTL (FO = 4) circuits.     

Small geometry depleted base bipolar transistors (BSIT)—VLSI devices?

An essential characteristic of devices which are viable candidates for VLSI circuits is that they must have electrical characteristics which can tolerate process variations. Conventional bipolar junction transistors (BJT) are well known to be limited by punchthrough when vertical basewidths axe decreased; these devices are, however, relatively tolerant of linewidth variations. The depleted base bipolar transistor represents a limiting case when the metallurgical basewidth is allowed to shrink to zero. Such devices, also called bipolar static induction transistors (BSIT), have been proposed as candidates for VLSI logic circuits. This paper describes the basic device physics of depleted base transistors and presents experimental verification of the theoretical modeling. The two essential conclusions that are drawn are that such devices can only achieve performance (in terms of transconductance) comparable to BJT's when an electrical p-type base exists (n-p-n device) and secondly, that BSIT's have characteristics which are extremely sensitive to process variations (linewidths, junction depths, and doping profiles). As a consequence, we conclude that while pure bipolar transistors may play an important role in VLSI circuits, depleted base structures such as the BSlT, are unlikely candidates for such applications.     

Self-aligned transistors with polysilicon emitters for bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. This leads to the formation of p⁺-n⁺junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p⁺-n⁺junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

Closed-form expressions for the coupling capacitance of metal fill tiles in VLSI circuits

A new closed-form formula for the computation of the coupling capacitance of metal tiles is presented in this work. It exploits the analytical solution of the Laplace equations of equivalent studied problems. Comparative results are given with two commercial tools employing the boundary element method (BEM) and the finite element method (FEM). The results show that the capacitance value computed by the proposed formula is in close agreement to the value obtained by the simulators.     

A model for charge transport in surface channel devices

A distributed capacitor model is proposed to simulate charge transport in surface inversion layers. Theoretical results of this model agreed well with experimental results obtained on the input section of a charge-coupled device (CCD).     

Numerical analysis and interpretation of the small-signalminority-carrier transport in bipolar devices

A simple and efficient one-dimensional numerical technique is presented that determines the small-signal minority-carrier transport in the quasineutral regions of bipolar devices, such as diodes and transistors, under sinusoidal excitation. The technique is applied to study small-signal properties of p-n junction diodes and bipolar transistors. Examples treated include the frequency dependence of transistor current gain, the diffusion capacitance of a quasineutral base or emitter, and base-layer carrier propagation delay     

Transconductance degradation in VLSI devices

Experimental results from small geometry VLSI devices show that as devices are scaled, transconductance degradation occurs. This results from scaling either the length or width. A model using a mobility expression developed by Wang is used to predict transconductance in small MOS devices. Comparison between theory and experiments is excellent.     

Near-field measurements of VLSI devices

This short paper describes a technique for the measurement of the electric near field at the package surface of microprocessors and other VLSI devices. The technique uses precision stepper motors for highly accurate placement of an electric field probe at the surface of the device to be measured. Structural resolution across the device is on the order of 400-600 μm. Typical scans accumulate 10000 data points across a variable scan area, which can be defined by device package dimensions or by the die dimensions. Characterizing a device involves a repeated series of surface scans at harmonics of the fundamental clock frequency. This paper describes the electric near field at the surface of a multichip module (MCM) composed of a processor, a flash memory, and application specific integrated circuit (ASIC). The MCM was measured while in operation in the actual circuit application     

Power bipolar devices

This paper deals with the specific aspects of bipolar device physics and with the problems posed by the design of their structure. Emphasis will be placed on the fundamental mechanisms which determine the on-state, the off-state and the switching performance. A number of relationships between operating characteristics and structure parameters are established. These relationships are useful for improving structure designs. The current-handling capability of high-voltage transistors is discussed thoroughly as a relevant example. Finally, the state of the art and trends of power bipolar devices are briefly reviewed.     

A 2D physically based compact model for advanced power bipolar devices

A two-dimensional (2D) physical compact model for advanced power bipolar devices such as Injection Enhanced Gate Transistor (IEGT) or Trench IGBT is presented in this paper. In order to model the complex 2D nature of these devices, the ambipolar diffusion equation has been solved simultaneously for different boundary conditions associated with different areas of the device. The IEGT compact model has been incorporated into the SABER simulator and tested in standard double-pulse switching test circuit. The compact model has been established to model a 4500 V-1500 A flat pack TOSHIBA IEGT.     

A process-oriented model for the simulation of base pushout in integrated bipolar devices

A closed-form solution to Poisson's equation applied to the base-collector region of an integrated bipolar device is developed. The solution comprises an extension to simplified analyses published elsewhere, and it leads to a process-oriented definition of base pushout phenomena, Moreover, the analytical results evolve into practical suggestions for effecting a high-injection simulation of gain and gain-bandwidth product characteristics.     

A simplified fully implanted bipolar VLSI technology

An implanted n-p-n bipolar transistor structure named Isoplanar Z II (currently, being marketed as FAST-Z technology) with reduced process and masking steps is described. The simplification is achieved by employing self-aligned-transistor (SAT) masking, ion-implantation techniques to provide impurity doping, and using one common annealing cycle for collector, base, and emitter implantations. The device structure reduces design constraints through use of self-aligned field implantation and SAT mask for contact window definition. Submicrometer emitter widths are obtained by step and repeat optical photolithographic tool and two-dimensional effect on current gain due to sidewall injection is also studied. This technology is used to demonstrate 13-15 ns TAA, 4K static RAM and minimum delay of 250 ps per gate, gate array products.     

Advancements in bipolar VLSI circuits and technologies

Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic and emitter-coupled logic are still mostly used, but new circuit technologies such as integrated injection logic or merged transistor logic and Schottky transistor logic or integrated Schottky logic have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly being replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected through technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 /spl mu/m dimensions or below.     

A physically based small-signal circuit model for heterostructureacoustic charge transport devices

A physically based small-signal circuit model for GaAs-AlGaAs Schottky gate heterostructure acoustic charge transport (HACT) devices is presented. Analytical expressions for the instantaneous and average channel current as a function of gate voltage are obtained from physical device parameters. The charge injection model is based on subthreshold current models for GaAs MESFETs. It is shown that the shape of the sampling aperture of the charge injection operation is approximately Gaussian. Good agreement is obtained between the measured DC channel current versus gate voltage and that predicted by the model. Equivalent circuits for the transfer and output sensing operations and expressions for noise sources due to the physical processes that occur within the device are developed. Thermal, shot, and transfer noise are treated. The form of the analytic expressions for frequency response and noise figure allows easy implementation on commercially available CAE software. Simulations of both gain and noise figure performed on Libra show good agreement with measured data