新型栅极结构的单色三极场发射器件

应用云母板作为栅极基底,结合常规的丝网印刷工艺,制作了改进的栅极结构。采用钙钠平板玻璃作为封装面板,利用碳纳米管作为冷阴极材料,研制了三极结构的单色场致发射显示器件。栅极基底的优良绝缘性能确保了其不易被强电场强度所击穿;改进的栅极层则能够进一步缩短栅极-阴极之间的有效距离,有利于降低栅极的工作电压。该显示器件具有高的显示亮度,良好的栅控能力以及场致发射特性。     

四针状纳米ZnO在场致发射显示器的应用研究

以高温气相氧化法制备的四针状纳米ZnO作为场致发射材料,采用浆料印刷和烧结的方法将其制备成场致发射阴极基板.将阴极板和荧光屏封装成5×25.4 mm二极结构的场致发射显示器,进行了场致发射特性实验,实现了稳定的场致电子发射及简单字符显示.该二极结构ZnO-FED的开启场强为1.5 V/μm,当场强为5.3 V/μm时,发射电流密度可达5.11 μA/cm2.通过实验测定场增强因子约为6 772,表现出了好的场致电子发射性能.实验结果表明了四针状纳米ZnO纳米材料是一种很好的场致发射阴极材料.     

新型前栅极CNT-FED的研究

传统的前栅极场致发射显示板由于介质层和栅极的制作在生成或制作阴极场致发射源之后，在制造过程中容易破坏场致发射源；另外阴极发射对介质层厚度、阳极电压和调制极开口等参数非常敏感，所以器件的发射均匀性难以保证。为了解决这些问题，引入了类似HOP玻璃的结构。阴极上只需要丝印碳纳米管，无需制作介质层和栅极，解决了场致发射源被破坏的问题。阴极与栅极之间真空取代了介质层，由于真空的绝缘性能高于介质层，所以阴极与栅极之间的距离可以减小，栅极的调制效果更显著。由于玻璃的平整度高于一般方法制作的介质层的平整度，所以器件的发射均匀性比较好。     

碳纳米管冷阴极电子枪的电子光学设计

基于皮尔斯电子枪设计理论,提出了一种碳纳米管场致发射阴极电子枪的电子光学设计方案。电子枪阴极半径为0.5 mm,保持阴阳极电压不变,动态调整栅极电压,并利用计算机技术仿真软件（CST）对其进行仿真优化研究;结果表明,栅极最佳电压值为-14 kV,对应阴极发射电流为15.08 mA,阳极处电子束半径约为0.1 mm。研究为碳纳米管冷阴极栅极结构的设计提供了一种新的思路。     

新型三极碳纳米管场发射器件的研究

采用催化剂高温分解方法制备了碳纳米管薄膜阴极。利用优质云母板作为绝缘材料．结合简单的丝网印刷工艺制作了新型的栅极结构。详细地给出了新型三极碳纳米管场发射器件的制作工艺．对场致发射的机理进行了初步的讨论。采用这种新型的栅极结构．不仅极大地降低了总体器件成本．同时避免了碳纳米管薄膜阴极的损伤．提高了器件的制作成功率。所制作的三极结构平板场发射器件具有良好的场致发射特性和栅极控制能力。     

基于InOx纳米岛／C的栅控薄膜电子发射阴极

介绍了基于InOx纳米岛／C的栅控薄膜电子发射阴极,并对其制备工艺和发射性能进行讨论。引入射频溅射的ZnO作为通道层,并在其上沉积InOx纳米岛以及无定型碳薄膜层。InOx纳米岛状结构引入了InOx／C复合活性层的不均匀性;在栅极以及源漏极电压的作用下,当有足够的传导电流通过InOx／C复合层时,通过电流热效应作用,复合层的某些导电通道被烧断,形成电子发射区域。本结构可以通过栅极电压来控制传导电流的有无,从而控制阴极电子发射的有无。     

高真空场发射三极显示器的制作

三极结构的场致发射显示器是一种新型的真空平板显示装置,高真空的实现与维持是确保显示器件正常工作的必要条件.通过采用低熔点玻璃粉烧结工艺和玻璃定位片装置,实现了场致发射显示器的高真空平板封装.从器件封装结构、器件烧结、器件排气和器件烤消等方面进行了工艺改进.综合采用这套技术,已经研发出三极结构的、具有高真空度的碳纳米管阴极场致发射显示器样品.     

楔型发射体真空微电子三级管的计算机模拟

本文利用广泛使用的ＰＩＣ粒子模拟软件ＭＡＧＩＣ模拟了楔型场致发射真空微电子三极管的一个单元的特性，该单元由一个楔型场致发射体，栅极和阳极组成。研究了栅极电压，阳极电压和发射体顶点半径等对发射电流的影响。给出了一个典型的楔型场致发射真空微电子三极管，当其阳极电压为５００Ｖ，阳极与阴极相距４μｍ时的电子轨迹图。模拟结果表明场致发射的栅极开启电压为２５０Ｖ。并得到了三极管高频工作时动力学特性。     

高亮度三极CNT-FED器件的研制

采用钠钙玻璃作为衬底材料,在常规丝网印刷工艺的基础上,设计制作了新型栅极-阴极组控制结构,实现了单条栅极对三个碳纳米管(CNT)阴极电子发射的成组控制。借助玻璃粉封接技术,研究了三极结构场致发射显示器件(FED)的封装和测试。结果表明,CNT-FED器件显示亮度高,阳极电压为1.6kV时,其最大亮度达710cd/m2;栅控特性良好,开启电压约为315V;显示的静态字符发光图像不仅证实了该器件的矩阵寻址功能已经实现,且具有良好的图形显示功能。     

低电子亲和势内场发射阴极

平面阴极的场致发射显示器件由于性能优越、结构简单而具有很好的应用前景。这种器件要实用化,急需提高阴极的电子发射率。提出一种改进栅极结构的方法达到提高电子发射率的目的;介绍了双金属栅极的结构和制作工艺;阐述了利用两种金属的接触电位差降低阴极电子发射势垒的原理;解释了实验中低驱动电压时发射率提高较多的现象。与单金属极相比双金属栅极的阴极电子发射率提高了5倍以上。     

RF LDMOS功率器件研制

基于ISE TCAD模拟软件对RF LDMOS器件的工艺流程和器件结构进行了优化设计,采用带栅极金属总线的版图结构降低栅电阻,同时简化了LDMOS器件的封装设计.通过实际流片和测试分析,重点讨论了漂移区注入剂量和漂移区长度对LDMOS器件的转移特性、击穿特性、截止频率及最大振荡频率的影响.测试结果表明该器件的阈值电压为1.8 V,击穿电压可达70 V,截止频率和最大振荡频率分别为9 GHz和12.6 GHz,并可提供0.7 W/mm的输出功率密度.     

一种P-GaN栅结合混合帽层结构的HEMT器件

为了进一步提升P-GaN栅HEMT器件的阈值电压和击穿电压,提出了一种具有P-GaN栅结合混合掺杂帽层结构的氮化镓高电子迁移率晶体管(HEMT)。新器件利用混合掺杂帽层结构,调节整体极化效应,可以进一步耗尽混合帽层下方沟道区域的二维电子气,提升阈值电压。在反向阻断状态下,混合帽层可以调节栅极右侧电场分布,改善栅边电场集中现象,提高器件的击穿电压。利用Sentaurus TCAD进行仿真,对比普通P-GaN栅增强型器件,结果显示,新型结构器件击穿电压由593 V提升至733 V,增幅达24%,阈值电压由0.509 V提升至1.323 V。     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

Simulation study on comparison between metal gate and polysilicongate for sub-quarter-micron MOSFETs

Two-dimensional (2-D) process and device simulation is used to investigate the effectiveness of the depletion-free metal gate for a sub-quarter-micron MOSFET as compared with surface channel polysilicon gate MOSFETs which suffer greatly from the gate depletion effect. The results reveal that the subthreshold characteristic for the metal gate NMOSFET is considerably degraded since the depletion-free merit is covered up by an undesirable influence of the buried channel structure, which is indispensable to obtain an appropriate threshold voltage for the midgap gate. Consequently, the drivability of the metal gate MOSFET is comparable to that of the heavily doped polysilicon gate MOSFET under commonly used conditions, and further, the metal gate structure is disadvantaged against the reduction of the supply voltage     

牵引用3 300 V平面栅IGBT栅极台面结构研究

针对机车牵引用3 300 V/1 500 A IGBT功率模块,采用TCAD仿真工具研究了不同栅极结构对器件静态和动态参数的影响。当平面栅IGBT采用栅极台面结构且台面厚度逐渐降低时,器件的静态阻断电压提高,开关损耗降低,但是器件的开关时间增加;此外,关断时过快的dv/dt会引起栅极电压振荡,开启时过快的di/dt会引起很大的电流过冲,导致器件应用的可靠性降低。在机车牵引的应用环境下,IGBT的栅极结构参数需要从电学参数和可靠性两个方面进行折中设计。     

三栅MOSFET阈值电压模型

根据三栅(TG)MOSFET二维数值模拟的结果,分析了TG MOSFET中的电势分布,得出了在硅体与掩埋层接触面的中心线上的电势随栅压变化的关系;通过数学推导,给出了基于物理模型的阈值电压的解析表达式;并由此讨论了多晶硅栅掺杂浓度、硅体中掺杂浓度、硅体的宽度和高度以及栅氧化层厚度对阈值电压的影响;得出在TG MOSFET器件的阈值电压设计时,应主要考虑多晶硅栅掺杂浓度、硅体中掺杂浓度和硅体的宽度等参数的结论。     

引入悬浮栅对有机薄膜晶体管的阈值电压进行调整

The structure of organic thin film transistors (OTFTs) is optimized by introducing floating gate into the gate dielectric to reduce the threshold voltage of OTFTs in this article. Then the optimized device is simulated and the results of the simulation show the threshold voltage of optimized device is reduced by about 10 V. The reduction of the threshold voltage is helpful and useful for the application of OTFTs in many areas. In addition, this way to reduce threshold voltage of OTFT is compatible with traditional silicon technology and can be used in manufacture.     

Threshold voltage adjustment of organic thin film transistor by introducing a polysilicon floating gate

The structure of organic thin film transistors (OTFTs) is optimized by introducing a floating gate into the gate dielectric to reduce the threshold voltage of OTFTs. Then the optimized device is simulated, and the simulation results show that the threshold voltage of optimized device is reduced by about 10 V. The reduction of the threshold voltage is helpful and useful for the application of OTFTs in many areas. In addition, this way of reducing the threshold voltage of OTFT is compatible with traditional silicon technology and can be used in manufacturing.     

New structure with SiO2-gate-dielectric select gates in vertical-channel three-dimensional (3D) NAND flash memory

This paper presents a novel vertical-channel three-dimensional (3-D) NAND flash structure with robust reliability. By employing a more reliable selector, the proposed structure overcomes the key drawback of the conventional 3-D NAND flash which is caused by charge storage in global select gate (GSG) and string select gate (SSG). Based on TCAD simulation, the conventional structure shows a threshold voltage shift of more than 1.5V, while the proposed structure is immune to this issue completely. Key parameters were analyzed to offer guidance on design and fabrication. Thickness of gate dielectric and thickness of SiO₂ spacing layer beneath GSG are key parameters for the electrical property of select gate, and thus should be designed accurately.