TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS

This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.     

Influence of defects in gate-oxide peripheral regions on the electrical characteristics of MOS structures

Radiation-induced defect formation is studied experimentally in the gate-insulator layer and at the semiconductor-insulator interface of NMOS and PMOS structures differing in perimeter-to-area ratio. The structures are fabricated by CMOS technology on the same n-Si wafer, the NMOS structures being formed in a p-well. Heavily phosphorus doped polysilicon and noncrystalline silicon dioxide are used as the gate and insulator materials, respectively. The devices considered are MOS varactors, MOS diodes, and MOSFETs. Capacitance-voltage characteristics are measured on the MOS varactors and diodes. The gate-voltage dependence is examined of surface conduction for the MOSFETs and the surface-recombination emitter-current component for the MOS diodes. The results are used to characterize defect formation in peripheral gate-oxide regions and the lightly doped part of the source (emitter) and the drain, as well as in the central gate-oxide region and at the Si/SiO₂ interface. The peripheral oxide regions are found to have a two-sided influence on the performance of the MOS structures. On the one hand, they act as a drain of uncombined hydrogen from the gate oxide, so that the effectiveness of defect deactivation by hydrogen depends on the perimeter-to-area ratio. On the other hand, the peripheral regions, particularly their corners, may have an elevated density of latent process-induced defects that can be activated by radiation, voltage, or thermal stress.     

Breakdown voltage characteristics of thin oxides and their correlation to defects in the oxide as observed by the EBIC technique

Thin oxides are widely used as the tunneling dielectric in floating gate EEPROM devices and as gate dielectric in short-channel MOS devices. The oxides are required to have high breakdown voltage and low defect density for reliable operation of the devices. With the Electron Beam Induced Current (EBIC) technique, defects in the oxide which lead to lower values of the oxide breakdown voltage have been observed.     

中子辐照下的6H-SiCpn结电特性分析

用中子辐照在６Ｈ－ＳｉＣｐｎ结中引入的复合中心和深能级陷阱解释了ＳｉＣｐｎ结辐照后电特性退化的现象,并推导了辐照后ＳｉＣｐｎ结理想因子与外加电压的关系,给出了ＳｉＣｐｎ结中子辐照电特性退化的模型,模拟结果和实验数据的对比说明关于ＳｉＣｐｎ结电特性退化的理论解释是正确的。     

SiC隐埋沟道MOS结构夹断模式下的C-V特性畸变

用数值和解析的方法研究了SiC隐埋沟道MOS结构夹断模式下C-V特性的畸变.隐埋沟道MOSFET中存在一个pn结,在沟道夹断以后,半导体表面耗尽区和pn结耗尽区连在一起,这时总的表面电容是半导体表面耗尽区电容和pn结电容的串联,使埋沟MOS结构的C-V特性发生畸变.文中通过求解泊松方程,用解析的方法分析了这种畸变发生的物理机理,并对栅电容进行了计算,计算结果与实验结果符合得很好.     

Implant dose monitoring by MOS C–V measurement

The most critical parameter for deep sub-micron MOS field effect transistors is the threshold voltage, which is highly dependent on processing specifically, the ion implanted channel dose. Monitoring the channel doping on product wafers is highly desirable and is a major issue for process engineers. MOS C–V methods are widely used for process ramp up and monitoring and MOS C–V doping profiling is an introduced method for monitoring of low dose implants. However, the failure of the depletion approximation in the near surface region implies that conventional MOS C–V measurements yield erroneous doping profiles in that region. Integrating MOS C–V doping profiles yields only a partial implant dose excluding the important near surface dose portion. Here, we report a new approach, which enables the determination of the entire implant dose, taking into account the crucial surface region. Moreover, the MOS threshold voltage can be obtained self-consistently. The method is also applicable to MOS structures with ultra thin gate oxides.     

The MOS inversion layer as a minority carrier injector

In this paper we report the first experimental demonstration of the concept of MOS inversion layer injection (ILI). The new physical concept is based on the use of a MOS inversion layer as a minority carrier injector as part of a dynamic junction. The carrier injection of such a junction is entirely controlled by the MOS gate. Moreover, when the gate potential is reduced under the MOS threshold voltage, the junction collapses ensuring a very efficient turn-off mechanism. Based on this concept we propose two novel lateral three-terminal structures termed inversion layer diode (ILD) and inversion layer bipolar transistor (ILBT). The concept of inversion layer injection can be applied in power devices where effective MOS gate control of the active junctions is important     

Imaging of the lateral GOI-defect distribution in silicon MOS wafers with lock-in IR-thermography

Yield and reliability of MOS devices are strongly affected by crystal-originated particles which may generate gate oxide integrity (GOI) defects. For the semiconductor industry it is highly desirable not only to measure the density, but also to image the lateral distribution of GOI-defects. A novel technique to image GOI defects across large gate areas has been developed. First, a low-ohmic bias pulse is used to break down nearly all GOI defects in a large-area MOS structure. Then a periodic bias of typically 2 V is applied and the local temperature variation caused by the leakage current through the broken GOI defects is imaged by lock-in IR-thermography. This technique has been used to image the GOI defect distribution across 8′′ Czochralski wafers. Various lateral variations of the defect distribution have been confirmed.     

DC characteristic simulation for floating gate neuron MOS circuits

An original approach to DC characteristic SPICE simulation for floating gate neuron MOS circuits is demonstrated. A novel macromodel which calculates the floating gate potential by combining resistances and dependent voltage and current sources is introduced. Utilising this method, DC characteristics for neuron MOS circuits have been confirmed to be successfully simulated using SPICE     

Charge accumulation and mobility in thin dielectric MOS transistors

A study of the turn-on of very thin dielectric MOS devices from subthreshold to strong inversion is described. A functional form has been found for the derivative of channel charge with respect to gate voltage, the derivative of channel charge with respect to distance along the channel, and the electric field along the channel in this transition region. A method to extract electron mobility versus gate voltage independent of any arbitrarily defined threshold voltage has been shown. Measured data on the electron mobility vs gate voltage for 100Å gate dielectric MOS devices are reported.     

Oxide current in MOS transistors operated under charge pumping conditions

The present paper describes an alternative approach for isolating the oxide current from the gate current (GC) and its use for characterizing the bulk oxide in MOS transistors. The method is based on measurements of the gate as well as the substrate currents of MOS transistors pulsed by a train of square wave pulses under charge pumping conditions.The measurements are done on various experimental devices and different gate and drain/source voltage biasing. The GC has been measured and was found to be of typical behavior when it is plotted with respect to the gate voltage. Moreover, the gate and substrate currents are found to be of complementary shapes when plotted with respect to gate voltage. This behavior is made useful in studying and characterizing the oxide and the interface of MOS transistors.     

放射状双pn结抑制片上电感衬底损耗

使用标准CMOS工艺,在放射状的n阱上面扩散p＋,使垂直和水平方向形成双pn结,将此结放在电感的底部用来抑制衬底损耗．提出并实验证明了该结构形成的高阻区厚度不是垂直pn结耗尽层的厚度,而是最低层的pn结的深度．首次通过接地的p＋扩散层屏蔽电感到衬底电场,水平和垂直pn结耗尽层厚度随着pn结反向偏压升高改变衬底有效的高阻区厚度,电感品质因数跟随高阻区厚度升降,有效地证明了pn结衬底隔离可以降低电感的衬底电流造成的损耗．     

放射状双pn结抑制片上电感衬底损耗

使用标准CMOS工艺,在放射状的n阱上面扩散p+,使垂直和水平方向形成双pn结,将此结放在电感的底部用来抑制衬底损耗.提出并实验证明了该结构形成的高阻区厚度不是垂直pn结耗尽层的厚度,而是最低层的pn结的深度.首次通过接地的p+扩散层屏蔽电感到衬底电场,水平和垂直pn结耗尽层厚度随着pn结反向偏压升高改变衬底有效的高阻区厚度,电感品质因数跟随高阻区厚度升降,有效地证明了pn结衬底隔离可以降低电感的衬底电流造成的损耗.     

In-process voltage stressing to increase reliability of MOS integrated circuits

Time-dependent dielectric breakdown of gate oxides is one of the principal failure mechanisms of MOS integrated circuits. Voltage stressing of completed devices, which has been used to screen oxide defects and to thereby increase product reliability, is less effective with scaled high-density MOS integrated circuits because of limitations in the voltage which can be applied. Inprocess voltage stressing of silicon wafers, prior to completion of wafer processing, offers a feasible technique for achieving an effective voltage screen. Several possible techniques for inprocess voltage stressing are described, and the advantages and limitations of these are outlined. Data are presented showing typical fast-ramp dielectric breakdown distributions for MOS transistor arrays with an oxide thickness of 35 and 50 nm. Time-dependent dielectric breakdown distribution data on devices from the same wafers indicate that with all MOS transistors of an integrated circuit connected in parallel, as in one type of inprocess voltage stressing, defective oxide sites can be screened in periods of time ranging from a few seconds to hours. Inprocess voltage stressing, by decreasing susceptibility of completed devices to time-dependent dielectric breakdown, can substantially increase MOS integrated circuit reliability.     

Extraction of the series resistance and the effective mobility in enhancement MOSFETs from weak to strong inversion using a single transistor

This work presents a new approach for the simultaneous determination of the effective channel mobility and the parasitic series resistance as a function of gate voltage in enhancement MOSFETs. The proposed method is applicable for short channel devices as well as long channel ones. It also takes into consideration the effect of interface traps and the dependence of the effective channel length on gate bias. The method is based on the measurement of the dynamic transconductance, gate-channel capacitance and the ohmic region drain current all on a single MOS transistors. The obtained results suggest a peak for the effective mobility versus gate voltage near threshold. The parasitic series resistance for short channel devices shows only slight dependence on the gate bias in the whole strong inversion region. On the contrary, for long channel devices, the series resistance significantly decreases with increasing gate voltage at the onset of strong inversion and then tends to level off as the device is pushed deeper in strong inversion.     

硅膜厚度对0.1μm SOI槽栅NMOS器件特性的影响

SOI技术和槽栅MOS新器件结构是在改善器件特性方面的两大突破,SOI槽栅MOS器件结构能够弥补体硅槽栅MOS器件在驱动能力和亚阈值特性方面的不足,同时也保证了在深亚微米领域的抑制短沟道效应和抗热载流子效应的能力.仿真结果显示硅膜厚度对SOI槽栅MOS器件的阈值电压、亚阈值特性和饱和驱动能力都有较大影响,选择最佳的硅膜厚度是获得较好的器件特性的重要因素.     

典型ESD防护器件失效机理研究

瞬态电压抑制管(TVS)是电子线路设计中常用的静电放电(ESD)防护器件,其可靠性将直接影响整个电路的安全。选取常见的TVS器件PESD5V0U1BA进行研究,通过实验和仿真分析了TVS器件的短路失效机理及其影响。研究表明,当TVS器件注入高压时,器件存在缺陷的SiO2层会发生自愈性击穿。当器件的pn结发生击穿时,器件将失效。如果两个pn结都被击穿,器件的I-V曲线表现为电阻特性。当TVS器件出现损伤后,器件仍具有箝位作用,且其表现的箝位电压更低,但由于器件的漏电流发生较大的增长,将影响被保护电路的正常工作。     

A new method to determine MOSFET channel length

A new method is proposed to electrically determine MOS transistor channel length with both accuracy and convenience. Based on the linear region relationship between effective channel length Leffand channel resistance Rchanof an MOS transistor, this method determines Leffby applying relatively large but constant gate voltage to eliminate threshold voltage determination and takes into account external resistance. Comparison of this method with SEM measurement shows very good agreement (within ±0.1 µm resolution limit of our SEM technique).     

Applications of synchronized switching in series-parallel-connectedJosephson junctions

It was found that series-parallel-connected Josephson junctions exhibit synchronized switching. The structure used makes possible a Josephson device with an output voltage equal to a multiple of the gap voltage. As a result one of the structures becomes almost the same as a direct-coupled-logic gate. However, multiple junctions are required and circuit parameters in the gate must be optimized for synchronized switching. In experiments, the synchronized switching of all junctions connected in series and parallel were demonstrated. A high-voltage gate was constructed using synchronized switching and was applied to a cell driver in a Josephson memory circuit. The output voltage was four times the gap voltage, and a fast access of 590 ps was obtained. Experimental results are described for three applications: a memory cell driver, a regulator, and an interface circuit     

The effects of impact ionization on the operation of neighboringdevices and circuits

This paper examines the detrimental effects of excess majority carriers and photons induced by impact ionization on the operation of neighboring pn junctions, bipolar transistors, MOS transistors, and circuits. The experimental results show that in addition to an increase in the substrate surface potential due to the excess majority carriers, photons can lower the barrier of a pn junction and, as a consequence, shift the Gummel plot of an npn bipolar transistor. As for the neighboring circuits, an example in which the speed of an NMOS ring oscillator is retarded by impact ionization in a neighboring NMOS transistor is presented