An analytical model for the lateral channel electric field in LDDstructures

An analytical model for the lateral channel electric field in lightly doped drain (LDD) MOSFETs is developed from a pseudo-two-dimensional analysis. The model gives a prediction of the channel field when the lightly doped region is both fully depleted and partially depleted. The normal field mobility degradation and variation of the saturation field E_sat with gate voltage have been taken into account in the model. The boundary conditions for determining the pinch-off point L_sat proposed in the model along with the normal field mobility degradation consideration make possible the prediction of the variation of the pinch-off with the gate bias and the maximum value of the electric field E_max . The differences between this model, existing models, and two-dimensional numerical simulations are discussed     

Silicon MOS transconductance scaling into the overshoot regime

Simulations incorporating velocity overshoot are used to derive the dependence of deep-submicrometer MOS transconductance on low-field mobility μ_eff and channel length L_ch. In contract to strict velocity saturation, saturated transconductance departs from a strict μ_eff/L_ch dependence when overshoot is considered. Constraints on μ_eff derived from conventional scaling laws together with strong μ _eff dependencies in these regimes indicate the importance of low-field inversion layer control and optimization. Transconductance in saturation is shown to approach a well-defined limit for very high μ _eff     

Gate-controlled negative differential resistance in drain currentcharacteristics of AlGaAs/InGaAs/GaAs pseudomorphic MODFETs

The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L _g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V_ds>2.5 V and V_gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V_gs<0 V resulting in f_max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V_gs >0 V and V_ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions     

Channel-length measurement technique based on a floating-gatedevice

By measuring the threshold voltage of the structure for several drawn channel lengths, ΔL is extracted. This technique is the translation of a capacitance measurement into a threshold measurement and as such is accurate and simple to perform. Since the technique does not involve a current flow through the transistor under test, it is especially advantageous for L_eff measurements on lightly-doped drain (LDD) and double-diffused drain (DDD) short-channel devices     

Scaling properties and short-channel effects in submicrometerAlGaAs/GaAs MODFET's: A Monte Carlo study

Scaling properties of n⁺-Al_xGa_1-xAs/GaAs MODFETs with submicrometer gate lengths (L_G=0.50 to 0.05 μm) are examined, using Monte Carlo methods. High-frequency performance of MODFETs can be improved by scaling the gate lengths, but various studies suggest that there exists a lower limit for the gate after which no improvement should be expected. The lower limit is determined here to be ≈0.10 μm. Devices with smaller gate lengths than 0.1 μm exhibit degraded transconductance (g_m), large shift in threshold voltage due to poor charge control in the channel, and a sharp reduction in output resistance (R_o). It is shown that the drain current saturation in MODFETs is not caused by the velocity saturation effect, but by channel pitch-off. Electron velocities calculated from Monte Carlo simulations and extracted from g_m and f_t measurements are reconciled     

The effect of fluorine on MOSFET channel length

The effect of fluorine on MOS device channel length has been evaluated. Fluorine has been introduced into the transistor by self-aligned ion implantation after the lightly doped drain (LDD) implant. The impact of fluorine in the LDD region, and its effect on the electrically determined channel length (L_eff), has been examined. Measurements taken from 0.6-μm LDD MOSFETs show a significant dependence of the L_eff on fluorine implant dose. The n⁺ resistor also shows more width reduction compared to unfluorinated samples. The decrease in channel length reduction by adding fluorine in the LDD region may yield way to relieve short-channel effects for the continuous scaling of CMOS devices into the deep-submicrometer region     

The effects of source/drain resistance on deep submicrometer deviceperformance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox =15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance     

Characteristics of field-induced-drain (FID) poly-Si TFTs with highon/off current ratio

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 10⁷ (V_d=10, V_g =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n⁺ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs     

Threshold voltage model for deep-submicrometer MOSFETs

The threshold voltage, V_th, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V_th on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V_th dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

High-performance dual-gate CMOS utilizing a novel self-alignedpocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi₂ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L_g (the physical gate length) is 0.21 μm for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21-μm gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5×10 ¹⁶ cm^-3). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 μm, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 μm     

Mobility profiles in short and narrow GaAs MESFET channels

Gate-voltage-dependent mobility profiles in long-, short-, wide-, and narrow-channel WN_x-BPLDD (buried p-type buffer lightly doped drain region) GaAs MESFETs have been determined (L_G =10, 4, 2, 1, 0.8, 0.5, 0.3 μm, W_G=20 μm; W_G-100, 40, 20, 10, 4, 2 μm, L _G=0.5 μm). The mobility mainly depends on the channel width, while the gate length has much less influence. Thus, using proper gate dimensions the channel mobility can be tuned. The highest drift mobility values agree quite well with the measured Hall mobilities. Mobility profiles of large-area MESFETs are probably degraded by the WN _x-gate fabrication process. Injected excess charges at gate length below 0.5 μm distorts the mobility evaluations     

Power-supply voltage impact on circuit performance for half andlower submicrometer CMOS LSI

Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E_cL_eff, where E_c is the critical electric field necessary to cause carrier velocity saturation and L_eff is the effective channel length, is introduced. Experimental results confirmed that 1.1E_cL_eff predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 μm). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E_cL_eff can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6-μm channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E_cL_eff     

Characteristics including electron velocity overshoot for0.1-μm-gate-length GaAs SAINT MESFET's

Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1-μm-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n⁺-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length ( a/L_g). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n⁺-layers. The average electron velocity for 0.1- to 0.2-μm-gate-length FETs is estimated to be 3×10⁶ cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f_T of 93.1 GHz has been attained by the 0.1-μm SAINT MESFET     

Two-dimensional numerical analysis of the minimum isolationdistance for GaAs digital large-scale integration

The minimum device isolation distance (L_min) applicable to GaAs digital large-scale integrated circuits is presented. The leakage current between two n-type layers formed in a semi-insulating (SI) substrate is simulated using a two-dimensional numerical model, and the results are compared with measurements. It is found that the leakage current is restricted by a potential hump formed by residual acceptors in the SI GaAs substrate when an isolating layer loses its compensated SI property. L_min is defined as the distance at which there is a leakage current of 1 mA for an isolating layer width of 1 cm. The calculated value of L_min at room temperature is 1.3 μm with a bias voltage of 2 V and an acceptor concentration of 10¹⁵ cm^-3. L_min decreases to 2/3 of this value when the temperature is reduced from 400 to 100 K, to 1/3 when the acceptor concentration is increased by one order, and to 2/3 when the bias voltage is reduced from 5 to 2 V     

A p-channel poly-Si/Si1-xGex/Si sandwichedconductivity modulated thin-film transistor

A p-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistor (CMTFT) is proposed and demonstrated in this paper for the first time. This structure uses a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide high on-state current. Results show that this structure provides high on-state current as well as low leakage current as compared to that of conventional offset drain TFTs. The on-state current of the structure is 1.3-3 orders of magnitude higher than that of a conventional offset drain TFT at a gate voltage of -24 V and drain voltage ranging from -15 to -5 V while maintaining comparable leakage current     

A self-aligned gate lightly doped drain (Al, Ga)As/GaAs MODFET

An asymmetrical lightly doped drain (LDD) (Al, Ga)As/GaAs modulation-doped FET (MODFET) structure with high drain-to-source and drain-to-gate breakdown voltages was fabricated. The LDD structure has a self-aligned lightly doped n^- region between the channel and a heavily doped n⁺ region at the drain, to reduce the electric field and impact ionization. The length of the lightly doped n ^- region on the drain side was varied from 0 to 1 μm. Drain-to-source breakdown voltage BV_ds improved from 4.6 to >10 V while the transconductance g_m remained unchanged. The drain-to-gate reverse breakdown voltage BV _dg increased from ≈7 to >20 V. The two breakdown mechanisms are believed to be independent. The LDD MODFET should find widespread application in circuits requiring high breakdown voltage such as high-speed analog-to-digital converters (ADCs) and microwave power amplifiers     

Doubly strainedIn0.41Al0.59As/n+-In0.65Ga0.35As HFET with high breakdown voltage

An In_0.41Al_0.59As/n⁺-In_0.65 Ga_0.35As HFET on InP was designed and fabricated, using the following methodology to enhance device breakdown: a quantum-well channel to introduce electron quantization and increase the effective channel bandgap, a strained In_0.41Al_0.59As insulator, and the elimination of parasitic mesa-sidewall gate leakage. The In_0.65Ga_0.35As channel is optimally doped to N_D=6×10¹⁸ cm^-3. The resulting device (L_g=1.9 μm, W_g =200 μm) has f_t=14.9 GHz, f_max in the range of 85 to 101 GHz, MSG=17.6 dB at 12 GHz V_B=12.8 V, and I_D(max)=302 mA/mm. This structure offers the promise of high-voltage applications at high frequencies on InP     

Current-gain cutoff frequency comparison of InGaAs HEMTs

The current-gain cutoff frequency performance of pseudomorphic InGaAs/AlGaAs (20% InAs composition) high-electron-mobility transistors (HEMTs) on GaAs is compared to that of lattice-matched InGaAs/InAlAs HEMTs on InP. The current-gain cutoff frequency (f_t) characteristics as a function of gate length (L_g) indicate that the f_t-L_g product of ~26 GHz-μm in InGaAs/InAlAs HEMTs is 23% higher than that of ~21 GHz-μm in InGaAs/AlGaAs HEMTs. The performance of InGaAs/AlGaAs HEMTs is also 46% higher than that of conventional GaAs/AlGaAs HEMTs (~18 GHz-μm). These data are very useful in improving the device performance of HEMTs for a given gate length     

Hot-electron-induced degradation of conventional, minimum overlap,LDD and DDD N-channel MOSFETs

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n^- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n⁺ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n^- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe