IC-compatible silicon wafer-to-wafer bonding

In this paper a fully IC-compatible silicon wafer-to-wafer fusion-bonding process is described. Before the bonding, the silicon surfaces are treated by chemicals which do not attack the electronic circuits or aluminium patterns on the silicon. The prebonding of the two silicon wafers is performed at room temperature. after which bonding takes place through annealing at temperatures between 120 and 400°C without affecting the performance of the electronic circuitry. The bonding is sufficiently strong for microsensor applications.     

Low temperature wafer bonding for thin silicon film transfer

In this work, we investigate the low temperature (<200 °C) wafer bonding using wet chemical surface activation and we demonstrate high bonding strength sufficient to achieve the transfer of a thin silicon film of thickness less than 400 nm on top of another silicon wafer using spin-on-glass (SOG) film as an intermediate layer. The process developed is the first critical step that can enable three-dimensional (3D) integration and wafer level packaging of MEMS with electronic circuits.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.

     

Adhesive bonding with SU-8 in a vacuum for capacitive pressure sensors

This paper describes a method for fabricating capacitive pressure sensors through the use of adhesive bonding with SU-8 in a vacuum. The influence of different parameters on the bonding of structured wafers was investigated. It was found that pre-bake time, pumping time, and the thickness of the crosslink layer are the most important factors for successful bonding. Bonding quality was evaluated by inspection through the transparent glass of the sensor and through the use of an SEM photograph, with 90% of the area successfully bonded and an ultimate yield of 70% of the sensors. The measured bonding strength was 17.15 MPa and 19.6 MPa for wafers bonded in 80 °C and 100 °C, respectively. The pressure–capacitance characteristic test results show that this bonding process is a viable micro electro mechanical systems (MEMS) fabrication technology for cavity sealing in a vacuum.     

Low-temperature wafer-level transfer bonding

In this paper, we present a new wafer-level transfer bonding technology. The technology can be used to transfer devices or films from one substrate wafer (sacrificial device wafer) to another substrate wafer (target wafer). The transfer bonding technology includes only low-temperature processes; thus, it is compatible with integrated circuits. The process flow consists of low-temperature adhesive bonding followed by sacrificially thinning of the device wafer. The transferred devices/films can be electrically interconnected to the target wafer (e.g., a CMOS wafer) if required. We present three example devices for which we have used the transfer bonding technology. The examples include two polycrystalline silicon structures and a test device for temperature coefficient of resistance measurements of thin-film materials. One of the main advantages of the new transfer bonding technology is that transducers and integrated circuits can be independently processed and optimized on different wafers before integrating the transducers on the integrated circuit wafer. Thus, the transducers can be made of, e.g., monocrystalline silicon or other high-temperature annealed, high-performance materials. Wafer-level transfer bonding can be a competitive alternative to flip-chip bonding, especially for thin-film devices with small feature sizes and when small electrical interconnections (<3×3 μm²) between the devices and the target wafer are required     

Room temperature bonding for vacuum applications: climatic and long time tests

A detailed and quantitative motivation for the necessity of room temperature (RT) bonding for wafer level packaging of silicon micro-mirrors will be given. Results on RT 6 inch wafer bonding with vacuum encapsulation on test structures are presented. Structured as well as unstructured wafers have been bonded at RT using a Mitsubishi Heavy Industries bonder. Unstructured wafers were used for the determination of the bonding strength, whereas the structured wafers were used for the evaluation of vacuum level and its stability with time.     

Characterization of low-temperature wafer bonding using thin-film parylene

This paper presents detailed experimental data on wafer bonding using a thin Parylene layer, and reports results on: 1) bond strength and its dependence on bonding temperature, bonding force, ambient pressure (vacuum), and time, 2) bond strength variation and stability up to two years post bond, and 3) bond strength variation after exposure to process chemicals. Wafer bonding using thin (<381 nm) Parylene intermediate layers on each wafer in a standard commercial bonder and aligner has been successfully developed. The Parylene bond strength is optimized at 230/spl deg/C, although Parylene bonding is possible at as low as 130/spl deg/C. The optimized bonding conditions are a low-temperature of /spl sim/230/spl deg/C, a vacuum of /spl sim/ 0.153 mbar, and 800 N force on a 100 mm wafer. The resultant Parylene bond strength is 3.60 MPa, and the strength for wafers bonded at or above 210/spl deg/C is maintained within 93% of its original value after two years. The bond strength is also measured after exposure to several process chemicals. The bond strength was reduced most in undiluted AZ400K (base) by 69% after one week, then in BHF (acid), MF319 (base), Acetone (solvent), and IPA (solvent) by 56%, 33%, 20%, and 8%, respectively, although less than one hour exposure to these chemicals did not cause a significant bond strength change (less than 11%). [1487].     

Influences of interface oxidation on transmission laser bonding of wafers for microsystem packaging

In the fabrication of micro-devices and systems, wafer bonding offers a unique opportunity for constructing complicated three-dimensional structures. In this paper, a wafer bonding technique, called transmission laser bonding (TLB), is studied with focus on the effects of interface oxidation and contact pressure on the bonding strength. The TLB is implemented for bonding Pyrex glass-to-silicon wafers, with and without interface oxide layers, using a Q-switch pulsed Nd:YAG laser. The tensile strengths of the TLB bonded specimens are comparable to those generated by the existing major wafer bonding techniques. The advantages of TLB are also discussed with some details. The oxide thickness is measured by spectro-reflectometry while the roughness of the oxidized surfaces is quantified using Atomic Force Microscopy (AFM). The bonded interfaces are analyzed by X-ray Photoelectron Spectroscopy (XPS) and Auger Electron Spectroscopy (AES) to study the migration and diffusion of different atoms across the bonding interface and to provide the necessary information for the understanding of the bonding mechanism. A thermal penetration analysis is also provided to validate the findings of the bond strength and spectroscopic evaluations.     

Low temperature wafer direct bonding

A pronounced increase of interface energy of room temperature bonded hydrophilic Si/Si, Si/SiO₂, and SiO₂/SiO ₂ wafers after storage in air at room temperature, 150°C for 10-400 h has been observed. The increased number of OH groups due to a reaction between water and the strained oxide and/or silicon at the interface at temperatures below 110°C and the formation of stronger siloxane bonds above 110°C appear to be the main mechanisms responsible for the increase in the interface energy. After prolonged storage, interface bubbles are detectable by an infrared camera at the Si/Si bonding seam. Desorbed hydrocarbons as well as hydrogen generated by a reaction of water with silicon appear to be the major contents in the bubbles. Design guidelines for low temperature wafer direct bonding technology are proposed     

Direct bonding with on-wafer metal interconnections

A low temperature direct bonding process with encapsulated metal interconnections was proposed. The process can be realized between silicon wafers or silicon and glass wafers. To establish well-insulated electric connection, sputtered aluminum film was patterned between a bottom thermal SiO₂ and a top PE-SiO₂; the consequential uneven wafer surface was planarized through a chemical mechanical polishing (CMP) step. Benefit from this smooth surface finish, direct bonding is achieved at room temperature, and a general yielding rate of more than 95% is obtained. Test results confirmed the reliability of the bonding. The main advantages of this new technology are its electric connectivity, low thermal stress and hermeticity. This process can be utilized for the packaging of micro electro mechanical system (MEMS) devices or the production of SOI wafers with pre-fabricated electrodes and wires.     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Discussion of tooling solutions for the direct bonding of silicon wafers

Silicon-to-silicon fusion (or direct) pre-bonding is an important enabling technology for many emerging microelectronics and MEMS technologies. A silicon–silicon direct bond can be easily formed, where the wafer surfaces are highly flat and very clean (Tong and Gosele), however for practical structured MEMS devices, wafer bow and local roughness may be compromised such that it is no longer a trivial task to achieve a direct bond. Tooling has been developed to facilitate the in situ alignment and bonding of silicon-to-silicon wafers in a vacuum chamber. The rate and direction of the bond propagation are controlled, thus minimising the occurrence of non-particle related voids. The tooling system also allows wafers with “non-ideal” surfaces or warped profiles to be bonded, by maximising the area across which bonding occurs and providing in situ annealing. The ability to anneal the wafers while maintaining clamping force creates attractive forces high enough to overcome the mechanical repulsive forces between the wafers and maintain a permanent bond. The tooling system can also be configured to give control over the bow or residual stress in the bonded pair, a factor that is critical in multi-stack direct wafer bonding.     

Versatile low temperature wafer bonding and bond strength measurement by a blister test method

We present a low temperature plasma assisted bonding process that enables the bonding of silicon, silicon oxide and silicon nitride wafers among each other at annealing temperatures as low as room temperature. The process can be applied using standard clean room equipment. Surface energies of differently treated bonded samples are determined by a blister test method for square shaped cavities. For this reason, we extend the well-known blister test method for round shaped cavities to the square shaped case by a combined analytical and numerical approach. Accordingly, the energetic favored crack front propagation in the bond interface is determined by numerical simulations. The surface energies of the tested samples are calculated and compared to anodic silicon-to-Pyrex^® bonds. Surface energies of up to 2.6 J/m² can be achieved between silicon and silicon oxide wafer pairs at low annealing temperatures. Room temperature bonded samples show a surface energy of 1.9 J/m². The surface energy of silicon-to-Pyrex glass bonds yields 1.3 J/m². Small structures, e.g., bridges down to 5 μm can be bonded using the discussed bonding process. Selective bonding of silicon-to-silicon oxide wafer pairs is performed by structuring the oxide layer. The successful integration of the bonding process into the fabrication of micropumps is highlighted.     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

Bond-quality characterization of silicon-glass anodic bonding

A simple testing method is presented that allows the comparison of the bond quality for anodically bonded wafers. An array of parallel metal lines of predetermined thickness is formed on a glass wafer. The estimation of the bond quality can be performed by visual inspection after the bonding. This method enables comparison of the anodic-bonding process performance for different glasses, for intermediate layers and various bonding conditions. The optimization of silicon-glass anodic bonding with an intermediate phosphosilicate glass (PSG) layer is shown using this technique.     

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

Non-destructive in situ test for anodic bonding

New test structures have been designed, fabricated and tested to monitor the quality of the anodic bonding between silicon and glass. The main advantage of the described test is that it is not destructive and allows the bond quality to be monitored in processed wafers. This test is very easy to implement in a chip or in a wafer because of its simplicity. Test structures consist of a matrix of circular and rectangular cavities defined by reactive ion etching (RIE) on the silicon wafer, with different sizes and depths. The bonding process and quality can be monitorized by the measurement of the size of the smallest bonded cavity and the distance between the bonded area and the cavity border. These structures give information about the level of electrostatic pressure that has been applied to pull together into intimate contact the surfaces of the two wafers. The higher the electrostatic pressure, the better the bond. We have applied these test structures to study the influence of the voltage and the temperature on the anodic bonding process. Results are in good agreement with finite-element method (FEM) simulations.     

Low temperature Si/Si wafer direct bonding using a plasma activated method

Manufacturing and integration of micro-electro-mechanical systems (MEMS) devices and integrated circuits (ICs) by wafer bonding often generate problems caused by thermal properties of materials. This paper presents a low temperature wafer direct bonding process assisted by O₂ plasma. Silicon wafers were treated with wet chemical cleaning and subsequently activated by O₂ plasma in the etch element of a sputtering system. Then, two wafers were brought into contact in the bonder followed by annealing in N₂ atmosphere for several hours. An infrared imaging system was used to detect bonding defects and a razor blade test was carried out to determine surface energy. The bonding yield reaches 90%–95% and the achieved surface energy is 1.76 J/m² when the bonded wafers are annealed at 350 °C in N₂ atmosphere for 2 h. Void formation was systematically observed and elimination methods were proposed. The size and density of voids greatly depend on the annealing temperature. Short O₂ plasma treatment for 60 s can alleviate void formation and enhance surface energy. A pulling test reveals that the bonding strength is more than 11.0 MPa. This low temperature wafer direct bonding process provides an efficient and reliable method for 3D integration, system on chip, and MEMS packaging.     

Fusion bonding of rough surfaces with polishing technique for silicon micromachining

 Surface roughness is one of the crucial factors in silicon fusion bonding. Due to the enhanced surface roughness, it is almost impossible to bond wafers after KOH etching. This also applies when wafers are heavily doped, have a thick LPCVD silicon nitride layer on top or have a LPCVD polysilicon layer of poor quality. It has been demonstrated that these wafers bond spontaneously after a very brief chemical mechanical polishing step. An adhesion parameter, that comprises of both the mechanical and chemical properties of the surface, is introduced when discussing the influence of surface roughness on the bondability. Fusion bonding, combined with a polishing technique, will broaden the applications of bonding techniques in silicon micromachining. Received 30 October 1996/Accepted: 14 November 1996