Reduced thermal strain in flip chip assembly on organic substrateusing low CTE anisotropic conductive film

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances, resulting in a high performance and cost-competitive packaging method. This paper describes the usefulness of low cost flip-chip assembly using electroless Ni/Au bump and anisotropic conductive films on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed as a low cost bumping method. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with Ni₃P precipitation above 300°C causes an increase of hardness and an increase of the intrinsic stress. As interconnection material, modified ACFs composed of nickel conductive fillers for conductive fillers, and nonconductive fillers for modification of film properties, such as coefficient of thermal expansion (CTE), were formulated for improved electrical and mechanical properties of ACF interconnection. Three ACF materials with different CTE values were prepared and bonded between Si chips and FR-4 boards for the thermal strain measurement using moire interferometry. The thermal strain of the ACF interconnection layer, induced by temperature excursion of 80°C, was decreased according to the decreasing CTEs of ACF materials. This result indicates that the thermal fatigue life of ACF flip chip assembly on organic boards, limited by the thermal expansion mismatch between the chip and the board, could be increased by low CTE ACF     

Filler size and content effects on the composite properties of anisotropic conductive films (ACFs) and reliability of flip chip assembly using ACFs

Flip chip assembly on organic board using anisotropic conductive films (ACFs) is gained more attention because of its many advantages. But to obtain more reliable flip chip assembly, it is necessary to have low coefficient of thermal expansion (CTE) value of ACFs. To control the CTE of ACF materials, non-conductive silica fillers were incorporated into ACFs. The effect of non-conductive silica filler content and size on cure kinetics and thermo-mechanical properties of ACFs was studied. Furthermore, filler content and size effects on reliability of flip chip assembly using ACFs were also investigated. In accordance with increasing filler content, curing peak temperature and storage modulus (E′) increased. But CTE decreased as the filler content increased. The effect of filler size on composite properties and assembly reliability showed similar tendency with the filler content effect. The smaller filler size was applied, the better composite properties and reliability were obtained. Conclusively, incorporation of non-conductive fillers, particularly in case of smaller size and higher content, in ACFs improves the material properties significantly, and as a result, flip chip assembly using ACFs is resulted in better reliability.     

Effect of nonconducting filler additions on ACA properties and thereliability of ACA flip-chip on organic substrates

We investigated the effect of nonconducting fillers on the thermomechanical properties of modified anisotropic conductive adhesive (ACA) composite materials and the reliability of flip chip assembly on organic substrates using modified ACA composite materials. For the characterization of modified ACAs composites with different content of nonconducting fillers, dynamic scanning calorimetry (DSC), thermogravimetric analysis (TGA), dynamic mechanical analysis (DMA), and thermomechanical analysis (TMA) were utilized. As the nonconducting filler content increased, CTE values decreased and storage modulus at room temperature increased. In addition, the increase in the content of filler brought about the increase of T_g(DSC) and T_g(TMA). However, the TGA behaviors stayed almost the same. Contact resistance changes were measured during reliability tests such as thermal cycling, high humidity and temperature, and high temperature at dry condition. The reliability results were significantly influenced by CTEs of ACA materials, especially at the thermal cycling tests. Results showed that flip chip assembly using modified ACA composites with lower coefficients of thermal expansion (CTEs) and higher modulus by loading nonconducting fillers exhibited better contact resistance behavior than conventional ACAs without nonconducting fillers     

Effects of silica filler and diluent on material properties and reliability of nonconductive pastes (NCPs) for flip-chip applications

In this paper, thermomechanical and rheological properties of nonconductive pastes (NCPs) depending on silica filler contents and diluent contents were investigated. And then, thermal cycling (T/C) reliability of flip chip assembly using selected NCPs was verified. As the silica filler content increased, thermomechanical properties of NCPs were changed. The higher the silica filler content was added, glass transition temperature (T/sub g/) and storage modulus at room temperature became higher while coefficient of thermal expansion (CTE) decreased. On the other hand, rheological properties of NCPs were significantly affected by diluent content. As the diluent content increased, viscosity of NCP decreased and thixotropic index increased. However, the addition of diluent deteriorated thermomechanical properties such as modulus, CTE, and T/sub g/. Based on these results, three candidates of NCPs with various silica filler and diluent contents were selected and used as adhesives for reliability test of flip chip assemblies. T/C reliability test was performed by measuring changes of NCP bump connection resistance. Results showed that flip chip assembly using NCP with lower CTE and higher modulus exhibited better T/C reliability behavior because of reduced shear strain in NCP adhesive layer.     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Processability and reliability of nonconductive adhesives (NCAs) in fine-pitch chip-on-flex applications

The use of NCAs to form direct contact interconnections between chip bumps and substrate pads have become a viable option in interconnection technology for fine-pitch applications. However, the primary concerns with NCAs are their long-term reliability, stability, and consistent electrical performance in particulate interconnections. Results of assembly process studies and environmental testing using NCAs on flexible substrates are analyzed and discussed herein. An extensive design experiment was performed to determine which process parameters were critical in obtaining good electrical connections. A reliability evaluation of NCAs for flexible substrate applications was carried out to gain more insight into the failure mechanisms of this type of interconnect. Pressure cooker test results showed that failures occurring in NCA joints are primarily due to moisture absorption, which could lead to interfacial delamination at the substrate/adhesive interface, accompanied by hygroscopic swelling. NCAs with lower coefficients of thermal expansion also exhibited better contact resistance stability during high-temperature storage tests.     

面向窄节距倒装互连的预成型底部填充技术

近年来随着电子产品的小型化发展,窄节距倒装芯片互连已经成为研究热点。传统的倒装芯片组装后底部填充技术(例如底部毛细填充)在用于窄节距互连时易产生孔洞,导致可靠性降低,因此产业界开发了面向窄节距倒装芯片互连的预成型底部填充技术,主要包括非流动底部填充和圆片级底部填充。介绍了这类新型底部填充技术的具体工艺及材料需求,并提出了目前其在大规模量产以及未来更窄节距应用中存在的问题及挑战,总结了目前产业界在提高量产生产效率、提升电互连的可靠性以及开发纳米级高热导率填料等方面提出的解决方案,分析了该技术未来的发展方向。     

Adhesion issues in flip-chip on organic modules

Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses     

Effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue lifetime significantly. The reliability of solder joint in flip chip assembly for both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Experimental results strongly showed that the thermal fatigue lifetime of solder joints in flip chip on flex assembly was much improved over that in flip chip on rigid substrate assembly. Debonding area of solder joints in flip chip on rigid board and flip chip on flex assemblies were investigated, and it was found that flex substrate could slow down solder joint crack propagation rate. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique. TMA results showed that flex substrate buckles or bends during temperature cycling and this phenomenon was discussed from the point of view of mechanics of the flip chip assembly during temperature cycling process. It was indicated that the thermal strain and stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Highly reliable, fine pitch chip on glass (COG) joints fabricated using Sn/Cu bumps and non-conductive adhesives

We have developed a reliable and ultra-fine pitch chip on glass (COG) bonding technique using Sn/Cu bumps and non-conductive adhesive (NCA). Sn/Cu bumps were formed by electroplating and reflowed, forming dome shaped Sn bumps on Cu columns. COG bonding was performed between the reflowed Sn/Cu bumps on the oxidized Si wafer and ITO/Au/Cu/Ti/glass substrate using a thermo-compression bonder. Three different NCAs were applied during bonding. Bonding temperature was 150 °C for NCA-A and NCA-B, and 110 °C for NCA-C. The electrical properties of COG joints were evaluated by measuring the contact resistance of each joint through the four-point probe method. All joints were successfully bonded and the electrical measurement showed that the average contact resistance of each joint was approximately 30 mΩ, regardless of NCA types. The COG joints were subjected to a series of reliability tests: high temperature storage test (85 °C, 160 h); thermal cycling test (−40 °C/+85 °C, 20 cycle); and a temperature and humidity test (50 °C/90%, 160 h) were sequentially performed to evaluate the reliability of the COG joints. The contact resistance measurement showed that there were no failed bumps in all specimens and all joints passed the criterion after reliability test.     

Bed of Nails—100- $mu$m-Pitch Wafer-Level Interconnections Process

The rapid advances in integrated chip (IC) design and fabrication continue to challenge electronic packaging technology, in terms of fine pitch, high performance, low cost, and reliability. Demand for higher input/output (I/O) count per IC chip increases as the IC chip fabrication technology is continuously moving towards nano ICs with feature size less than 90 nm. As micro systems continue to move towards high speed and microminiaturization technologies, stringent electrical and mechanical properties are required. To meet the above requirements, chip-to-substrate interconnection technologies with less than 100-mum pitch are required. Currently, the coefficient of thermal expansion (CTE) mismatch between the Si chip and the substrate serves as the biggest bottleneck issue in conventional chip to substrate interconnections technology, which becomes even more critical as the pitch of the interconnects is reduces. Further, the assembly yield of such fine-pitch interconnections also serves as one of the biggest challenges. Bed-of-nails (BoN) interconnects show great potential in meeting some of these requirements for next-generation packaging. In the present study, BoN interconnects prepared by a novel process called copper column wafer-level packaging is presented. The BoN interconnect technology is being developed to meet fine pitch of 100 mum and high-density interconnections. These BoN interconnects are demonstrated by designing a test chip of 10times10mm²size with 3338 I/Os and fabricated using an optimized process. The board-level reliability tests performed under temperature cycling in the range of -40degC to 125degC show promising results.     

Characterization of lead-free solders and under bump metallurgies for flip-chip package

A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications. When coupled with underfill encapsulation in a direct chip attach (DCA) test device, the Sn-0.7Cu bump with Cu UBM exhibits a characteristic life or 5322 cycles under -55/spl deg/C/+150/spl deg/C air-to-air thermal cycling condition.     

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.     

Research on the contact resistance,reliability, and degradation mechanisms of anisotropically conductive film interconnection for flip-chip-on-flex applications

Although there have been many years of development, the degradation of the electrical performance of anisotropically conductive adhesive or film (ACA or ACF) interconnection for flip-chip assembly is still a critical drawback despite wide application. In-depth study about the reliability and degradation mechanism of ACF interconnection is necessary. In this paper, the initial contact resistance, electrical performance after reliability tests, and degradation mechanisms of ACF interconnection for flip-chip-on-flex (FCOF) assembly were studied using very-low-height Ni and Au-coated Ni-bumped chips. The combination of ACF and very-low-height bumped chips was considered because it has potential for very low cost and ultrafine pitch interconnection. Contact resistance changes were monitored during reliability tests, such as high humidity and temperature and thermal cycling. The high, initial contact resistance resulted from a thin oxide layer on the surface of the bumps. The reliability results showed that the degradation of electrical performance was mainly related to the oxide formation on the surface of deformed particles with non-noble metal coating, the severe metal oxidation on the conductive surface of bumps, and coefficient of thermal expansion (CTE) mismatch between the ACF adhesive and the contact conductive-surface metallization. Some methods for reducing initial contact resistance and improving ACF interconnection reliability were suggested. The suggestions include the removal of the oxide layer and an increase of the Au-coating film to improve conductive-surface quality, appropriate choice of conductive particle, and further development of better polymeric adhesives with low CTE and high electrical performance.     

Material properties of anisotropic conductive films (ACFs) and their flip chip assembly reliability in NAND flash memory applications

In this paper, the material properties of anisotropic conductive films (ACFs) and ACF flip chip assembly reliability for a NAND flash memory application were investigated. Measurements were taken on the curing behaviors, the coefficient of thermal expansion (CTE), the modulus, the glass transition temperature (T_g), and the die adhesion strength of six types of ACF. Furthermore, the bonding processes of the ACFs were optimized. After the ACF flip chip assemblies were fabricated with optimized bonding processes, reliability tests were then carried out. In the pressure cooker test, the ACF with the highest adhesion strength showed the best reliability and the ACF flip chip assembly revealed no delamination at the chip-ACF interface, even after 96 h. In the high temperature storage test and the thermal cycling test, the reliability of the ACF flip chip assembly strongly depends on the T_g value of the ACF. In the thermal cycling test, in particular, which gives ACF flip chip assemblies repetitive shear stress, high value of CTE above T_g accelerates the failure rate of the ACF flip chip assembly. From the reliability test results, ACFs with a high T_g and a low CTE are preferable for enhancing the thermal and thermo-mechanical reliability. In addition, a new double-sided chip package with a thickness of 570 μm was demonstrated for NAND flash memory application. In conclusion, this study verifies the ACF feasibility, and recommends the optimum ACF material properties, for NAND flash memory application.     

Double bump flip-chip assembly

Capillary underfill remains the dominate process for underfilling Hip-chip die both in packages and for direct chip attach (DCA) on printed circuit board (PCB) assemblies. Capillary underfill requires a post reflow dispense and cure operation, and the underflow time increases with increasing die area and decreasing die-to-substrate spacing. Fluxing or no-How underfills are dispensed prior to die placement and cure during the solder reflow cycle. Since filler particles in the fluxing underfill can be trapped between the solder ball and the substrate pad during placement, the filler content of fluxing underfills is typically limited to <20% or assembly yield drops dramatically. At 20% filler concentration, the coefficient of thermal expansion (CTE) of the underfill is near that of the bulk resin (50-80 ppm//spl deg/C). In this paper, a double bump Hip-chip process is described. A filled capillary underfill is coated onto a wafer and cured. The wafer is then polished to expose the solder bumps. A second solder bump is formed over the original bump by stencil printing solder paste. After dicing, the die is assembled to the PCB using unfilled fluxing underfill. In the resulting structure, the low CTE underfill is near the low CTE Si die, and the higher CTE underfill is in contact with the PCB. In addition, the standoff height is increased compared to a conventional single bump assembly. In air-to-air thermal shock tests, the double bump assembly was /spl sim/ 1.5 X more reliable than the conventional single bump construction with fluxing underfill. Modeling results are also presented.     

Reliability study of underfill/chip interface under accelerated temperature cycling (ATC) loading

Interface reliability issue has become a major concern in developing flip chip assembly. The CTE mismatch between different material layers may induce severe interface delamination reliability problem. In this study, multifunctional micro-moiré interferometry (M³I) system was utilized to study the interfacial response of flip chip assembly under accelerated thermal cycling (ATC) in the temperature range of −40 °C to 125 °C. This in-situ measurement provided good interpretation of interfacial behavior of delaminated flip chip assembly. Finite element analysis (FEA) was carried out by introducing viscoelastic properties of underfill material. The simulation results were found to be in good agreement with the experimental results. Interfacial fracture mechanics was used to quantify interfacial fracture toughness and mode mixity of the underfill/chip interface under the ATC loading. It was found that the interfacial toughness is not only relative to CTE mismatch but also a function of stiffness mismatch between chip/underfill.     

Development of a mathematical model for thermal-compression bonding of the COG packaging process using NCA

In this decade, many new techniques have been introduced into the integrated circuit (IC) packaging industry. Packaging technology used in liquid crystal displays (LCDs) has requirements related to critical issues such as high density interconnects, thinner packaging size, and environmental safety. Driver IC chips are directly attached to LCD panels using flip chip technology with adhesives in the so called chip on glass (COG) packaging processes. To investigate the dependence of the bonding force on the bump deformation during packaging, this study established a mathematical model to analyze COG packaging processes with non-conductive adhesives (NCAs). The plastic deformation of the bumps and the NCA flow between the chip and substrate are taken into account in this model. With this model, the contact resistance and the gap height after bonding can be estimated for different bonding force.     

Effects of Heating Rate on Material Properties of Anisotropic Conductive Film (ACF) and Thermal Cycling Reliability of ACF Flip Chip Assembly

In this paper, the effects of heating rate during anisotropic conductive film (ACF) curing processes on ACF material properties such as thermomechanical and rheological properties were investigated. It was found that as the heating rate increased, the coefficient of thermal expansion (CTE) of the ACF increased, and the storage modulus and glass transition temperature $(T _{g})$ of the ACF decreased. Variation of the ACF material properties are attributed to cross-linking density, which is thought to be related with the ACF density. In addition, as the heating rate increased, the minimum viscosity of the ACF decreased and the curing onset temperature increased during the curing process. The similar phenomenon was also found in in-situ contact resistance measurement. As the heating rate increased, contact resistance establishing temperature increased and the contact resistances of the ACF flip chip assemblies decreased. The decrease in contact resistance was due to larger conductive particle deformation which leads to larger electrical contact area. The effect of the heating rate of ACFs on thermal cycling (T/C) reliability of flip chip assemblies was also investigated. As the heating rate increased, the contact resistances of the ACF flip chip assembly rapidly increased during the T/C test. The T/C reliability test result was analyzed by two terms of shear strain and conductive particle deformation. Reduced gap of joints due to reduced ACF viscosity resulted in larger shear strain. Moreover, many cracks were observed at metal-coated layers of conductive particles due to larger deformation.