22?Bit三阶Cascaded结构Sigma?Delta 调制器设计

设计一款可用于称重传感器ADC的高精度2?1级联结构Sigma?Delta调制器。在考虑非理想因素的前提下,采用Matlab/Simulink数学建模和仿真表明,在信号带宽为20 Hz,过采样率为1024的情况下,该调制器的信噪比为170.7 dB。采用Charter 0.35μm工艺对该调制器进行电路级设计并用Spectre仿真,电路信噪比为144.8 dB,该结果高于22位要求的135 dB。     

采用 DWA技术的多位Σ-Δ调制器的设计

设计一个内部采用2位量化器的二阶单环Σ‐Δ调制器．为解决反馈回路中多位DAC元件失配导致的信号谐波失真问题,该调制器采用了数据加权平均（Data Weighted Averaging ,DWA ）技术来提高多位DAC的线性度．Σ‐Δ调制器信号带宽为50 kHz ,过采样率（OSR）为64,采用MXIC公司的0．35μm混合信号CMOS工艺实现,工作电压为12 V ．后仿真结果显示,在电容随机失配5％的情况下,该调制器可以达到55．8 dB的信噪比（SNR）和60.4 dB的无杂散动态范围（SFDR）．打开DWA电路比关闭DWA电路的情况下,SNR和SFDR分别提高8 dB和13 dB ．整个调制器功耗为48 mW ,面积仅为0.6mm2．     

2-1-1级联连续时间型ΣΔ调制器系统设计

高阶连续时间型ΣΔ调制器提供了一种有效的获得高分辨率、低功耗模数转换器的方法.提出了一种新型的2-1-1级联的连续时间型ΣΔ调制器结构.采用冲激不变法将离散时间型ΣΔ调制器变换为连续时间型ΣΔ调制器,利用Simulink对该调制器进行系统级建模和仿真,峰值信噪比达到105dB.分析了电路的非理想因素对调制器行为的影响,以获得90dB信噪比为目标确定了电路子模块指标.仿真结果表明,该结构能有效降低系统功耗,并验证了电路的可行性.     

一种16位delta-sigma调制器的设计与实现

文章介绍了一个应用于低频信号测量,3．3V单电源供电,信噪比达到96．7dB的低功耗的开关电容delta-sigma调制器的设计。根据delta—sigma结构理论以及实际应用范围,论证了采用cascade2-1结构3阶delta—sigma调制器的可行性,使得整个三阶结构的稳定输入范围等效于二阶调制器。文章采用自顶向下的设计方法,用simulink对3阶cascade2—1模型进行了系统级仿真,系统仿真加入了白噪声、闪烁噪声等各种低频噪声模型作为约束条件,通过精心调试仿真得到了各模块的指标。采用CSMC0．5μm双多晶三层金属工艺。主要模块包括积分器、比较器,并进行仿真验证,并与预定要求进行比较对照。文章在过采样率为256,采样频率为100kHz情况下对整个调制器电路进行了仿真,与系统仿真进行对照,能够达到16位的精度。整个调制器的静态功耗为1．7mW。     

一种高阶1 bit插入式∑-△调制器的设计

介绍了插入式∑-△ A/DC调制器的设计过程,并给出了调制器行为级SIMULINK模型,通过对调制器系统级仿真可以确定调制器的信噪比、增益因子等参数,为其电路设计提供依据.设计了一个4阶调制器,仿真结果显示在128的过采样比、输入信号相对幅度-6 dB的条件下,可获得110 dB的信噪比,达到18 bit的分辨率.     

应用于无线传感网络 SOC的低功耗∑△调制器

提出了一种应用于无线传感网络 SOC过采样率（OSR）为128的单环三阶单比特量化∑△调制器．通过采用新型前馈结构,降低了系统对运算放大器性能的要求;通过采用新颖的两级Class A/AB运算放大器实现积分器电路,有效降低了电路的功耗;为了进一步降低电路功耗,对调制器中的第二级、第三级运放进行了缩放．该调制器采用华虹0．18μm CMOS工艺,输入信号带宽为8 kHz ,工作电压1．8V ．后仿真结果表明：在输入信号频率为5 kHz、采样时钟为2．048 M Hz时,调制器的信噪比（SNR）达到96dB ,整个调制器的功耗仅为180μW ,芯片总面积为0．51 mm2．     

基于音频应用的四阶带宽可重构的Delta Sigma调制器

本文提出一种应用于音频领域的单环四阶Delta Sigma调制器,采用可重构机制以适用于两种基于带宽的模式（8kHz/16kHz）。该芯片采用SMIC 0.13μm CMOS 混合信号工艺,功耗为153.6μW,占用面积0.98*0.46mm2。该调制器在16kHz模式下,性能达到89.3dB的信噪比（SNR）和90.2dB的动态范围（DR）;在8kHz模式下,性能达到90.2dB的信噪比（SNR）和86dB的动态范围（DR）。所设计的调制器的优值（FOM）同近几年来的低压调制器比较具有很大的竞争力。     

一种应用于无线通信的低电压低功耗∑-D调制器的设计

文章首先分析了低电压对于低功耗CMOS∑-△调制器设计提出的挑战，使用了自顶向下的设计策略，利用Hapiee和Simulink对开关电客放大器和开关电路非理想特性建模．通过Matlab优化低功耗结构的运算放大器电路参数，最后给出了系统仿真结果。仿真结果显示。使用0．18μm 2p6m CMOS工艺设计的∑-△调制器在1．5V低电源电压条件下，信号带宽为200KHz，峰值信噪比达到93．5dB，动态范围为96．3dB，满足了GSM／PCSl800／DCSl900等无线应用的要求。     

一种14位、1．4MS／s、多位量化的级联型∑△调制器

在0.6μm CMOS工艺条件下设计了一种适合DECT(Digital Enhanced Cordless Telephone)标准的1.4MS／sNyquist转换速率、14位分辨率模数转换器的∑△调制器。该调制器采用了多位量化的级联型(2—1—1 4b)结构，通过Cadence SpectreS仿真验证，在采样时钟为25MHz和过采样率为16的条件下，该调制器可以达到86．7dB的动态范围，在3．3V电源电压下其总功耗为76mW。     

D类功放中的∑-△调制器分析与设计

设计一种新型低非线性失真拓扑的7阶1-bit∑-△调制器,该调制器可以直接用于模拟音频信号输入带反馈的D类功率放大器中。通过仿真表明,调制器的最大稳定输入值可以达到0．9,信噪比可达到130dB以上,即采用这种调制器的D类功放可实现90％的功率转化效率和高保真的音质。同时从新的角度阐释了高阶1-bit∑-△调制器的工作原理和设计过程。     

A re-configurable MASH 2-2 bandpass DQEFM for multi-standard applications

The design, analysis and implementation of a multi-stage noise shaping (MASH) bandpass modulator that employs a differentially quantized error feedback modulator (DQEFM) structure is described. The re-configurability, reduction of power-hungry active blocks and reduced sensitivity to circuit non-idealities makes this proposed bandpass modulator a suitable candidate for a digital intermediate frequency receiver system. The mathematical analysis and simulation results indicate the resemblance of the proposed modulator with the conventional sigma-delta modulator. The circuit level simulations indicate the better performance of the proposed modulator in terms of hardware complexity and power. The proposed cascaded modulator when implemented using 45nm CMOS process attains a signal-to-noise plus distortion ratio of 81.4 dB for a bandwidth of 200 kHz (GSM) and 61 dB for a bandwidth of 5 MHz (WCDMA). The circuit level simulation of the proposed bandpass architecture indicates a power consumption of 3.7 mW and 6.9 mW for GSM and WCDMA modes with 1V supply.     

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software     

高阶模拟Σ-Δ调制器设计研究

在简要介绍高阶1位量化Σ-ΔA/D转换器基本原理的基础上,分析了Σ-Δ调制器的噪声特性;介绍了传统线性模型下的噪声传递函数的设计方法。同时,结合实际高阶模拟Σ-Δ调制器的开关电容实现电路,重点对影响调制器性能的非理想因素进行了详细分析,并采用程序建模仿真的方法指导电路设计。与传统设计方法的结果对比表明,文中的方法可以为电路设计提供更加可靠的依据。     

A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/Dconversion

The authors examine the application of oversampling techniques to analog-to-digital conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta (ΣΔ) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding stringent component matching requirements is introduced. Issues concerning the design and implementation of the modulator are presented. At a sampling rate of 50 MHz and an oversampling ratio of 24, an implementation of the modulator in a 1-μm CMOS technology achieves a dynamic range of 74 dB at a Nyquist conversion rate of 2.1 MHz. The experimental modulator is a fully differential circuit that operates from a single 5-V power supply and does not require calibration or component trimming     

Design of a wideband low-power continuous-time ΣΔ modulator in 90 nm CMOS technology

The design of a wideband low-power continuous-time (CT) sigma-delta modulator (ΣΔM) is presented. At system level, an improved direct design method is used which allows direct design of the modulator in continuous-time domain. The modulator employs a low-latency flash quantizer to minimize excess loop delay. Digital-to-analog (DAC) trimming technique is used to correct the quantizer offset error, which permits minimum-sized transistors to be used for fast and low-power operation. The modulator is designed in 90 nm CMOS process with single 1.0-V power supply. It achieves a dynamic range (DR) of 75 dB and a signal-to-noise-and-distortion-ratio (SNDR) of 70 dB in a 25 MHz signal bandwidth with 16.4 mW power dissipation.     

Design Methodology for ΣΔM

The paper presents a design methodology based on correspondence between performance requirements, mathematical parameters, and circuit parameters of a sigma-delta modulator. This methodology will guide a design engineer in selecting the circuit parameters based on system requirements, in translating paper design directly into LSI design, in predicting the effect of component sensitivity, and in analyzing the operations of the sigma-delta modulator. The sigma-delta modulator is viewed as a device which distributes the noise power, determined by peak SNR, over a much broader band, compared to signal bandwidth, shapes and amplifies it, and allows filtering of the out-of-band noise. The shaping and amplification are quantified by two parameters,FandP, whose product is analogous to the square of step size of a uniform coder. These two parameters are related, on one hand, to the time constants or location of zero and poles. On the other hand, inequalities are set up between performance parameters, like signal-to-noise ratio and dynamic range, andFandP.     

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator.A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator.The proposed modulator uses sampling capacitor sharing switched capacitor integrator,and achieves a very small feedback coefficient by a series capacitor network,and those two techniques can dramatically reduce capacitor area.Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation.This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and-1 MHz IF with 48 MHz clock.The chip is fabricated with SMIC 0.18 μm CMOS technology,it achieves a total power current of 2.1 mA,and the chip area is 0.48 mm2.     

Sigma-Delta调制及其在低噪声DC-DC变换器的应用

分析了传统PWM调制和Sigma-Delta调制在噪声性能方面的差异,以及它们对DC-DC变换器输出噪声的影响。在Chartered 0.35μm CMOS工艺条件下实现了一个基于二阶Sigma-Delta调制的低噪声DC-DC变换器,并对其中Sigma-Delta调制模块进行了流片验证。测试结果表明,Sigma-Delta调制模块能够将环路带宽内噪声抑制到-50 dB左右,并且未引入与开关频率有关的谐波成分。仿真结果表明,DC-DC变换器输出电压噪底能够达到-60 dB以下。     

A robust CMOS compander

A robust CMOS compander circuit meeting all of the requirements for analog cellular telephony and using an improved sigma-delta compander topology is presented. Rather than digitizing and reconstructing the input signal using a sigma-delta modulator as has been done previously, only the amplitude path is digitized while the voice path remains analog. The amplitude information is obtained digitally, and is reduced to a single bit using a first-order sigma-delta modulator. Performing this function digitally eliminates problems due to analog offsets and in implementing the long time constant required. The output signal is formed by gating the analog input signal under control of the amplitude signal. The expander and compressor circuits each consist of a single op amp and 2000 gates of digital logic, and have been implemented on 0.8-μm CMOS processes. The ADC for the amplitude path uses a compact switched-capacitor second-order sigma-delta modulator implemented using a single amplifier. No external components are required. Tracking error for the compressor was measured to be less than 0.3 dB over a 60-dB input range when operating on a 3.0-V supply. The test time, when compared to conventional compander implementations, is considerably reduced     

一种0.18m单层多晶硅CMOS音频-调制器

设计了一种应用于18位高精度音频模数转换器(ADC)的三阶Σ-Δ调制器。调制器采用2-1级联结构,优化积分器的增益来提高调制器的动态范围。采用栅源自举技术设计输入信号采样开关,有效提高了采样电路的线性度。芯片采用中芯国际0.18μm混合信号CMOS工艺,在单层多晶硅条件的限制下,采用MIM电容,实现了高精度的Σ-Δ调制器电路。测试结果表明,在22.05kHz带宽内,信噪失真比(SNDR)和动态范围(DR)分别达到90dB和94dB。