A High-Swing, High-Speed CMOS WTA Using Differential Flipped Voltage Followers

A high-performance CMOS winner-take-all circuit based on the differential flipped voltage follower is introduced. Simulations demonstrate the potential of the circuit to operate at very high speed, with high precision even for close input values and with low supply voltages. Experimental verification of the circuit is provided in a 0.5-mum CMOS technology.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

PDP驱动芯片用RSDS接口电路设计

介绍了一种基于RSDS(减小摆幅差分信号传输)信号传输标准的PDP驱动芯片用接口电路设计,它包括PMOSFET输入CMOS差分放大器和电压源偏置电路.文章重点讨论了PMOSFET输入CMOS差分放大器的差模工作原理及影响其差模增益的因素.Spectre仿真结果表明,本文设计的RSDS接受器电路在输入信号频率为200 MHz的情况下能正常工作,实现了由RSDS信号转换为LVCMOS信号的功能.目前该接口电路已经应用于一款PDP驱动芯片中,作为高速数据传输接口.     

低延迟低电压电流比较器

设计了一种基于改进共源共栅电流镜的CMOS电流比较器,该比较器在1 V电压且电压误差±10%的状态下都正常工作,同时改进后的结构能够在低电压下取得较低的比较延迟。电路的输入级将输入的电流信号转化为电压信号,电平移位级的引入使该结构能够正常工作在不同的工艺角和温度下,然后通过放大器和反相器得到轨对轨输出电压。基于SMIC 0.18μm CMOS工艺进行了版图设计,并使用SPECTRE软件在不同工艺角、温度和电源电压下对电路进行了仿真。结果表明,该电路在TT工艺角下的比较精度为100 nA,平均功耗为85.53μW,延迟为2.55 ns,适合应用于高精度、低功耗电流型集成电路中。     

一个0.9V低电压双端输出第二代电流传输器的设计

介绍一个0.9 V低电压双端输出第二代电流传输器(DOCCⅡ)的设计。输入级采用衬底驱动MOSFET有效地避免了阈值电压的限制;同时采用了局部正反馈技术提高了带宽增益,因此DOCCII获得了更好的电压跟随特性。该设计电路在标准0.18μm CMOS工艺下,采用Cadence Spectre和BSIM3v3模型对其进行了调试和仿真。仿真结果显示该DOCCII具有4.8MHz的带宽,同时具有比较高的线性度和很好的输入输出电阻。     

高线性低电压低噪声放大器的设计

研究了一种具有高线性的CMOS低噪声放大器,其工作电压可以低于1V.在这个电路中,加一个工作在线性区的辅助MOS管以提高线性特性.仿真表明这种方法可以提高输入三阶交截点,其代价远小于传统方法为获得1dB线性度改善而必须增加1dB功耗的代价.为了降低该电路中的共栅PMOS管的有载输入阻抗,不使其源极处的电压增益过大而降低电路的线性特性,必须优化其尺寸.仿真使用的模型是TSMC 0.18μm射频CMOS工艺库,仿真工具是Cadence的SpectreRF.     

Compound current conveyor (CCII+ and CCII-)

A CMOS current conveyor configurable as CCII⁺ and/or CCII^- is proposed. The circuit has the advantages of providing two symmetrical outputs, presenting a low input resistance and giving a high output to input resistance ratio. An input resistance of 28 Ω with a zero at 6 MHz in a 0.5 μm implementation with a supply voltage of 3.3 V have been obtained     

An adaptive high-voltage protection and common-mode adjustment circuit for passive–active continuous-time sigma–delta ADCs

A digitally-programmable circuit is proposed to provide high-voltage protection at start-up, overload, and supply loss conditions in continuous-time passive–active sigma delta ADCs implemented in low-voltage nanometer CMOS technologies. The circuit optimizes the common-mode level at the input stage of the ADC enabling it to interface with input levels beyond its own supply voltage with no impact on device reliability or distortion levels, and minimum impact on area and noise performance, which provides maximum flexibility in the ADC usage. The proposed circuit along with the full ADC is implemented in a typical 65 nm CMOS technology.     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

Compact implementation of high-performance CMOS current mirror

A high-performance compact current mirror implementation with very low input resistance, very high output resistance, high copying accuracy, low input and output voltage supply requirements and high bandwidth is proposed. The circuit characteristics are validated with simulations in 0.5 /spl mu/m CMOS technology and with experimental results.     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

一种适用于Buck型DC/DC变换器的高精度片上电流采样电路

电流采样电路作为电流控制的DC/DC变换器重要组成部件之一,其精度和响应速度已受到越来越高的重视.提出的电流采样电路没有使用运算放大器,简化了电路结构,降低了功耗.同时,电路中引入的补偿电流进一步提高了采样的精度.基于0.5μm CMOS工艺实现该电路,HSPICE模拟仿真结果表明该电路具有较高的采样精度,最高可达99.9%,且在负载、输入电压、温度变化时,采样精度波动很小.     

High-speed dynamic reference voltage (DRV) CMOS/ECL interfacecircuits

This paper introduces a circuit technique to increase the operating speed of CMOS/ECL interface circuits. The technique is based on shifting the reference voltage dynamically to follow the ECL input signal. HSPICE simulation results based on a 0.8-μm BiCMOS technology show the advantages of DRV CMOS/ECL in terms of speed and noise margins. An analytical delay model which fits HSPICE simulation results is addressed. The error between the model and the circuit simulator is within 4%     

1.5 V four-quadrant CMOS current multiplier/divider

A low voltage CMOS four-quadrant current multiplier/divider circuit is presented. It is based on a compact V-I converter cell able to operate at very low supply voltages. Measurement results for an experimental prototype in a 0.8 /spl mu/m CMOS technology show good linearity for a /spl plusmn/15 /spl mu/A input current range and a 1.5 V supply voltage.     

1.2V 6GHz 1.19mW 32/33前置分频器的设计

基于4/5双模SCL分频结构设计了一个高速、低压、低功耗的32/33双模前置分频器。该设计基于TSMC90nm1P9M CMOS工艺,利用Mentor Graphics Eldo工具仿真,结果表明该分频器最高工作频率达6GHz,在电源电压1.2V,输入6GHz情况下,功耗仅1.19mW。     

Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements

This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistor's threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input-output voltage requirements, 100-/spl Omega/ input resistance, and more than 200-M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1.2-V supply in a standard CMOS technology.     

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

正A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC(automatic gain control) and a current-mode adaptive filter.Compared with its conventional voltage-mode counterparts,the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic.The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss.The continuous gain should meet the requirement of any input amplitude level,while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL(sound pressure level).Furthermore,the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility.These features can accommodate users whose ears have different pain thresholds.Taking advantage of the current-mode technique,the MOS transistors work in the subthreshold region so that the quiescent current is small.Moreover,the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain.Therefore,the objective of low voltage and low power(48μW at 1.4 V) can be easily achieved in a high threshold-voltage CMOS process of 0.35μm(V_(TON) + |V_(TOP)|≈1.35 V).The THD is below -45 dB.The fabricated chip only occupies the area of 1×0.5 mm~2 and 1×1 mm~2.     

Low‐Voltage CMOS Current Feedback Operational Amplifier and Its Application

A novel low‐voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail‐to‐rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ±0.75 V with a total standby current of 304 µA. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ±1 mA. An application of the CFOA to realize a new all‐pass filter is given. PSpice simulation results using 0.25 µm CMOS technology parameters for the proposed CFOA and its application are given.