Cost/Quality Trade-off in Synthesis for BIST

This paper details our allocation for Built-in Self Test (BIST) technique used by the core part of our Testability Allocation and Control System (TACOS) called IDAT. IDAT tool objective is to fulfill the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a test controller for the final testable circuit. The allocation process of BIST resources in the data-path is driven by two trade-off techniques performed in order to: (1) at the local level, select the optimal set of Functional Units (FUs) to be BISTed, using a new testability analysis method and (2) at the global level, for each selected FU of this set, choose either to allocate its BIST version (when available in a library) or to connect it to an internal Test Pattern Generator (TPG) and Test Results Checker (TRC). When necessary, a last step of the process is the allocation of scan chains used to test the remaining untested interconnections. Experiments show the results of our allocation for BIST technique on three benchmarks.     

ALADIN: a multilevel testability analyzer for VLSI system design

In order to cope with tomorrow's challenges in the microelectronic market, the reliability of the first phases of the design process must be improved. The possibility of applying techniques for testability analysis at these abstract design levels can considerably help in achieving this goal, reducing at the same time system design costs. In this paper we introduce a novel approach for the application of functional testability at system design level and demonstrate the possibility of its application in an industrial environment. Testability conditions referring to both regular and irregular topologies have been defined, formalized and inserted into the knowledge base of the expert system, ALADIN. This tool operates as a testability analyzer able to identify critical areas for testability in designs whose functional modules and local interconnections are known and described in standard VHDL. The architecture of the tool has been defined in order to satisfy the users' requirements including the integrability into a standard CAD design flow through standard I/O interfaces. Then its application to both a regular and an irregular topology are presented in order to show on real examples which testability conditions apply, and how the tool operates in order to reach the testability assessment. From these industrial case studies, figures of merit are derived from which it is possible to evaluate the importance of the application of such a methodology to system level design     

Linking design and test tools: an implementation

A computer-aided test analysis system was designed to appraise the testability of logic systems and to provide the functional specification of the test programs. To provide a helpful tool for both designers and test engineers, it was necessary to fully integrate this tool in a CAD (computer-aided design) system so that testability might be a design parameter and to automate the test-program production. The authors present the link between this tool and the SILVAR LISCO design system     

基于模型的综合模块化航电系统测试性设计方法

针对综合模块化航电系统对测试性提出的更高要求及其工程实践中存在的典型问题,定义了一种分布-集中式的系统测试诊断架构,以适应其体系架构的特点和生产配套关系的变化;提出了一种基于模型的系统测试性设计方法和流程,以测试性模型为驱动指导航电系统的测试性方案设计、评估与优化过程,取代传统的基于指标的测试性设计方法。在某机载综合射频系统上开展了方法应用,成功解决了该系统综合化以后测试诊断架构设计与测试性分配的非线性问题。     

深亚微米ASIC设计中的时序约束与静态时序分析

在现代深亚微米专用集成电路(ASIC)设计流程中,为使电路性能达到设计者的预期目标,并满足电路工作环境的要求,必须对一个电路设计进行诸如时序、面积、负载等多方面的约束,并自始至终使用这些约束条件来驱动电路设计软件的工作.文中介绍了设计中所需考虑的各种时序约束,并以同步数字系列(SDH)传输系统中8路VC12-VC4 E1映射电路设计为例,详细说明了设计中所采用的时序约束,并通过静态时序分析(STA)方法使电路时序收敛得到了很好的验证.     

基于MBSE的微波统一测控系统测试性设计

针对当前微波统一测控系统研制中存在的测试性要求宽松、测试性设计模式落后的问题,通过综合权衡可靠性、维修性和保障性的各项要求和约束条件,确定了微波统一测控系统的测试性定量要求,并对开展测试性定量设计和验证的可行性进行了论证;采用系统工程设计思想,将测试性设计和功能设计融合,构建了基于模型的系统工程（Model-based Systems Engineering,MBSE）的测试性设计环境和设计流程,可为微波统一测控系统在数字化研制过程中开展测试性设计和仿真验证提供参考。     

一种面向板级电路的故障注入系统设计

在装备测试性验证过程中,故障注入是一项关键技术。针对于装甲装备测试性设计不足的情况,利用已有实验条件,通过对电路中故障进行分类,设计实现了对应的模拟故障板,对某型坦克炮控系统中的电路板进行了故障注入,用故障检测设备检测到故障的存在,通过分析测试性验证数据,为装备BIT研究以及测试性设计的提高提供了依据。     

Research on the Efficiency Improvement of Design for Testability Using Test Point Allocation

Traditional design for testability (DFT) is arduous and time-consuming because of the iterative process of testability assessment and design modification. To improve the DFT efficiency, a DFT process based on test point allocation is proposed. In this process, the set of optimal test points will be automatically allocated according to the signal reachability under the constraints of testability criteria. Thus, the iterative DFT process will be completed by computer and the test engineers will be released to concentrate on the system design rather than the repetitive modification process. To perform test point allocation, the dependency matrix of signal to potential test point (SP-matrix) is defined based on multi-signal flow graph. Then, genetic algorithm (GA) is adopted to search for the optimal test point allocation solution based on the SP-matrix. At last, experiment is carried out to evaluate the effectiveness of the algorithm.     

某型军用测试设备可测试性设计验证

在某型军用测试设备设计的初期就考虑可测试性要求,通过优化系统结构并以方便测试为目的进行系统设计,通过故障树的方法从系统层面对测试设备的可测试性进行分析并验证,可为其它测试设备的研制提供参考.     

A design for testability approach for nano-CMOS analogue integrated circuits

Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker.     

Securing Scan Control in Crypto Chips

The design of secure ICs requires fulfilling means conforming to many design rules in order to protect access to secret data. On the other hand, designers of secure chips cannot neglect the testability of their chip since high quality production testing is primordial to a good level of security. However, security requirements may be in conflict with test needs and testability improvement techniques that increase both observability and controllability. In this paper, we propose to merge security and testability requirements in a control-oriented design for security scan technique. The proposed security scan design methodology induces an adaptation of two main aspects of testability technique design: protection at protocol level and at scan path level. Without loss of generality, the proposed solution is evaluated on a simple crypto chip in terms of security and design cost.

Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model.In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.     

Efficient probe selection algorithms for fault diagnosis

Increase in the network usage for more and more performance critical applications has caused a demand for tools that can monitor network health with minimum management traffic. Adaptive probing has the potential to provide effective tools for end-to-end monitoring and fault diagnosis over a network. Adaptive probing based algorithms adapt the probe set to localize faults in the network by sending less probes in healthy areas and more probes in the suspected areas of failure. In this paper we present adaptive probing tools that meet the requirements to provide an effective and efficient solution for fault diagnosis for modern communication systems. We present a system architecture for adaptive probing based fault diagnosis tool and propose algorithms for probe selection to perform failure detection and fault localization. We compare the performance and efficiency of the proposed algorithms through simulation results.     

基于DDR IP核视频图像缓存的设计与实现

在现代图像采集显示系统中,常常需要用到大容量、高速度的存储器,DDR为当前存储器应用的主流.采用了64 bit数据位宽的DDR IP核利用DDR的双倍数据传输速度的优点并结合了双口RAM的高速缓存特点,基于Ahera公司的Cyclone Ⅲ系列FPGA开发板在两种平台下实现了数据传输和图像缓存,并使用逻辑分析仪Sign...     

一种LED灯串故障自检测电路的设计与实现

LED背光模组因其具有诸多优势已经成为液晶显示器背光方式的主要选择,而在实际应用当中,若某串LED故障,液晶显示器就会出现暗线,导致亮度均匀性不能满足要求。为了保证液晶显示器的亮度均匀性和后期的维修效率,LED灯串需具备故障自检测的能力。本文设计了一种基于DSP的LED背光模组中灯串故障自检测电路,以546mm(21.5in)液晶显示器的直下式LED背光模组为例,设计了灯板、驱动板的具体硬件电路,利用CCS3.1开发工具,C语言编写软件控制逻辑。自检测结果表明:该电路可有效的对LED灯串进行故障自检测,满足了设计的要求。     

基于Xilinx PCI Express Core的高速DMA读写设计

本设计在基于Xilinx Virtex-6 FPGA内嵌PCI Express Core的基础上,实现了由PCI Express板卡主动发起的DMA读写,可完成PC和PCI Express板卡之间数据的高速传输。该设计已经在Xilinx评估板ML605上完成调试验证,DMA写内存速度稳定可达1 520 MB/s,满足了高速存储系统的要求。     

BCSESE:基于概念结构的专家系统开发环境

本文描述了一个用概念结构表示知识并推理的专家系统开发环境的设计与分析．它提供了概念图的显示图、线性图和内部表示等多种知识获取工具，具有对概念图的编辑、运算、推理和解释功能，为用户提供了一个界面友善的交互式集成开发环境。     

基于故障仿真和粗糙集的复杂电路板测试性分析

针对关联模型在复杂电路板测试性分析中对不确定问题描述与分析的缺陷,提出了基于故障仿真和粗糙集的测试性分析方法.通过故障仿真生成条件属性集,利用粗糙集将其约简,最终形成分辨矩阵,从而评价电路的测试性水平.最后通过实例分析验证了方法的有效性.     

一种基于多重模糊有向图的系统划分方法

在系统级测试性设计中,为了实现模块间合理划分,采用多重模糊有向图表示系统模块间的故障传播关系,并在此基础上实现了系统划分。该划分方法不仅充分考虑了系统可测性设计要求,而且将同一模块上的固有故障传播和传递得到的故障分开分析,建立更加接近实际的故障传播影响度矩阵,与其他方法相比,该方法更加贴近模块间故障影响的真实情况,能够实现更精确的系统划分。