Effects of electron irradiation on SiGe devices

The degradation and the recovery behavior of the device performance for SiGe diodes and p-MOSFETs irradiated by 2-MeV electrons are reported. For diodes, it is noted that both the reverse and forward current increase by irradiation. An interesting observation is that the forward current decreases after irradiation for a forward voltage larger than ~ 0.7 V. This reduction can be explained by an increased resistivity of the Si substrate. The degradation recovers by thermal annealing after irradiation. For a fluence of 1 × 10¹⁵ e/cm², the diode performance almost recovers to the initial condition after 250 °C annealing. For the transistors, after irradiation, a slight negative shift of the threshold voltage and a decrease of the drain current for input and output characteristics have been observed together with a decrease of hole mobility. This is mainly due to the increase of the threshold voltage induced by positive charge trapping in the gate oxide.     

Mobility of holes in a Si/Si0.8Ge0.2/Si metal oxide semiconductor field effect transistor

Using all standard scattering mechanisms the hole mobility in a metal oxide semiconductor field effect transistor SiGe conduction channel at 17 K and room temperature was calculated. The mobility measurements were performed at different bath temperatures in the range of 4-300 K. The 4 K peak mobility at a sheet carrier concentration, n_h, of 2.1 × 10¹¹ cm^− 2 is 5100 cm² V⁻¹ s^− 1 while the 300 K mobility has a peak value of 350 cm² V⁻¹ s^− 1. By comparing between theory and measurements it is shown that the interface impurities and surface roughness more strongly limit the mobility than alloy scattering does.     

Extended deep level defects in Ge-condensed SiGe-on-Insulator structures fabricated using proton and helium implantations

SiGe-on-Insulator (SGOI) structures were created using the Ge condensation method, where an oxidation process is performed on the SiGe/Si structure. This method involves rapid thermal chemical vapor deposition and H⁺/He⁺ ion-implantations. Deep level defects in these structures were investigated using deep level transient spectroscopy (DLTS) by varying the pulse injection time. According to the DLTS measurements, a deep level defect induced during the Ge condensation process was found at 0.28 eV above the valence band with a capture cross section of 2.67 × 10^− 17 cm², two extended deep levels were also found at 0.54 eV and 0.42 eV above the valence band with capture cross sections of 3.17 × 10^− 14 cm² and 0.96 × 10^− 15 cm², respectively. In the SGOI samples with ion-implantation, the densities of the newly generated defects as well as the existing defects were decreased effectively. Furthermore, the Coulomb barrier heights of the extended deep level defects were drastically reduced. Thus, we suggest that the Ge condensation method with H⁺ ion implantation could reduce deep level defects generated from the condensation and control the electrical properties of the condensed SiGe layers.     

Removal of stacking faults in Ge grown on Si through nanoscale openings in chemical SiO2

Nucleation and eventual coalescence of Ge islands, grown out of 5 to 7 nm diameter openings in chemical SiO₂ template and epitaxially registered to the underlying Si substrate, have been shown to generate a low density of threading dislocations (?10⁶ cm^− 2). This result compares favorably to a threading dislocation density exceeding 10⁸ cm^− 2 in Ge films grown directly on Si. However, the coalesced Ge film contains a relatively high density of stacking faults (5 × 10⁷ cm^− 2), and subsequent growth of GaAs leads to an adverse root-mean-square roughness of 36 nm and a reduced photoluminescence intensity at 20% compared to GaAs grown on Ge or GaAs substrates. Herein, we find that annealing the Ge islands at 1073 K for 30 min before their coalescence into a contiguous film completely removes the stacking faults. However, the anneal step undesirably desorbs any SiO₂ not covered by existing Ge islands. Further Ge growth results in a threading dislocation density of 5 × 10⁷ cm^− 2, but without any stacking faults. Threading dislocations are believed to result from the later Ge growth on the newly exposed Si where the SiO₂ has desorbed from areas uncovered by Ge islands. The morphology and photoluminescence intensity of GaAs grown on the annealed Ge is comparable to films grown on GaAs or Ge substrates. Despite this improvement, the GaAs films grown on the annealed Ge/Si exhibit a threading dislocation density of 2 × 10⁷ cm^− 2 and a minority carrier lifetime of 67 ps compared to 4 to 5 ns for GaAs on Ge or GaAs substrates. A second oxidation step after the high temperature anneal of the Ge islands is proposed to reconstitute the SiO₂ template and subsequently improve the quality of Ge film.     

Comparison of Ohmic contact resistances of n- and p-type Ge source/drain and their impact on transport characteristics of Ge metal oxide semiconductor field effect transistors

We report the results of a systematic study to understand low drive current of Ge-nMOSFET (metal-oxide-semiconductor field-effect transistor). The poor electron transport property is primarily attributed to the low dopant activation efficiency and high contact resistance. Results are supported by analyzing source/drain Ohmic metal contacts to n-type Ge using the transmission line method. Ni contacts to Ge nMOSFETs exhibit specific contact resistances of 10^− 3-10^− 5 Ω cm², which is significantly higher than the 10^− 7-10^− 8 Ω cm² of Ni contacts to Ge pMOSFETs. The high resistance of Ni Ohmic contacts to n-type Ge is attributed mainly to insufficient dopant activation in Ge (or high sheet resistance) and a high tunneling barrier. Results obtained in this work identify one of the root causes of the lower than expected Ge nMOSFET transport issue, advancing high mobility Ge channel technology.     

Electrical characterization of high-k gate dielectrics on Ge with HfGeN and GeO2 interlayers

Two kinds of HfSiO_x/interlayers (ILs)/Ge gate stack structures with HfGeN- and GeO₂-ILs were fabricated using electron cyclotron resonance (ECR) plasma sputtering and the subsequent post deposition annealing (PDA). It was found that HfGe was formed by the deposition of Hf metal on Ge and changed to HfGeN by N₂ ECR-plasma irradiation, which was used as IL. Another IL was GeO₂, which was grown by thermal oxidation at 500 °C. For dielectrics with HfGeN-IL, PDA of 550 °C resulted in effective oxide thickness (EOT) of 2.2 nm, hysteresis of 0.1 V, and interface state density (D_it) = 7 × 10¹² cm^− 2 eV^− 1. For dielectrics with GeO₂-IL, PDA of 500 °C resulted in EOT of 2.8 nm, hysteresis of 0.1 V, and D_it = 1 × 10¹² cm^− 2 eV^− 1. The structural change of HfSiO_x/GeO₂/Ge during the PDA was clarified by using X-ray photoelectron spectroscopy, and the gate stack formation for obtaining the good IL was discussed.     

Nitrogen-doped p-type ZnO thin films and ZnO/ZnSe p-n heterojunctions grown on ZnSe substrate by radical beam gettering epitaxy

We investigate the p-type doping in ZnO prepared by the method of radical beam gettering epitaxy using NO gas as the oxygen source and nitrogen dopant. Secondary ion mass spectroscopy measurements demonstrate that N is incorporated into ZnO film in concentration of about 8 × 10¹⁸ cm^− 3. The hole concentration of the N-doped p-type ZnO films was between 1.4 × 10¹⁷ and 7.2 × 10¹⁷ cm^− 3, and the hole mobility was 0.9-1.2 cm²/Vs as demonstrated by Hall effect measurements. The emission peak of 3.312 eV is observed in the photoluminescence spectra at 4.2  of N-doped p-type ZnO films, probably neutral acceptor bound. The activation energy of the nitrogen acceptor was obtained by temperature-dependent Hall-effect measurement and equals about 145 meV. The p-n heterojunctions ZnO/ZnSe were grown on n-type ZnSe substrate and have a turn-on voltage of about 3.5 V.     

Electrical characterization of wafer-bonded Ge(111)-on-insulator substrates using four-point-probe pseudo-metal-oxide-semiconductor field-effect transistor method

The electrical properties of wafer-bonded n-type Ge(111)-on-insulator (Ge(111)-OI) substrates were characterized using a four-point-probe pseudo-metal-oxide-semiconductor field-effect transistor (pseudo-MOSFET) method. Average electron and hole mobilities in the Ge(111)-OI channel were measured to be ~ 1000 cm²/V s in accumulation mode and ~ 310 cm²/V s in inversion mode, respectively. The measured mobility strongly depended on the sample position, due to the spatially inhomogeneous distribution of the interface states. Despite the existence of interface states, the carrier mobility exhibited a high value demonstrating the prospect of wafer-bonded Ge(111)-OI as a channel material in MOSFETs.     

Improved dielectric and ferroelectric properties in Ti-doped BiFeO3-PbTiO3 thin films prepared by pulsed laser deposition

Ti-modified thin films of multiferroic 0.72Bi(Fe_1 − xTi_x)O₃-0.28PbTiO₃ (BFPT, x = 0 and 0.02) solid solution were prepared by pulsed laser deposition. The BFPT (x = 0 and 0.02) films possess a tetragonal structure with highly preferential (001) orientation. The effects of the ionic substitution on the properties of BFPT (x = 0 and 0.02) films have been investigated. The leakage current of the BFPT (x = 0.02) thin film is significantly reduced, and the dielectric and ferroelectric properties greatly improved by the aliovalent ionic substitution of Ti⁴⁺ for Fe³⁺. The BFPT (x = 0.02) thin film exhibits a reasonably high remnant polarization P_r with 2P_r up to 90 μC/cm² at 312 kV/cm and a switchable polarization up to 92 μC/cm² at 417 kV/cm.     

Influence of SiGe layer thickness and Ge fraction on compressive strain and hole mobility in a SiGe-on-insulator substrate fabricated by the Ge condensation technique

Both compressive strain (ε_c) and hole mobility (μ_h) were investigated for SiGe-on-insulator substrates with different values for the SiGe layer thickness (d) and Ge fraction (Ge%), which were fabricated by Ge condensation. We found that the ε_c introduced during Ge condensation was strongly dependent on d and Ge%. Thinner d is helpful for maintaining higher ε_c when Ge% is 50%. ε_c is dramatically relaxed with a further increase in Ge%. By varying the tradeoff between Ge% and ε_c, we achieved a maximum μ_h of approximately 570 cm²/V·s in the d range of 9-11 nm and Ge% range of 50-65%.     

High performance infra-red detectors based on Si/SiGe multilayers quantum structure

Recently, single crystalline (Sc) Si/SiGe multi quantum structure has been recognized as a new low-cost thermistor material for IR detection. Higher signal-to-noise (SNR) ratio and temperature coefficient of resistance (TCR) than existing thermistor materials have converted it to a candidate for infrared (IR) detection in night vision applications. In this study, the effects of Ge content, C doping and the Ni silicidation of the contacts on the performance of SiGe/Si thermistor material have been investigated. Finally, an uncooled thermistor material with TCR of −4.5%/K for 100 μm × 100 μm pixel sizes and low noise constant (K_1/f) value of 4.4 × 10⁻¹⁵ is presented. The outstanding performance of the devices is due to Ni silicide contacts, smooth interfaces, and high quality multi quantum wells (MQWs) containing high Ge content.     

Source/drain junction fabrication for Ge metal-oxide-semiconductor field-effect transistors

We established fabrication methods for high-quality Ge n⁺/p and p⁺/n junctions using thermal diffusion of P and implantation of B, respectively. The carrier concentrations in n⁺ and p⁺ layers were as high as 4 × 10¹⁹ and 2 × 10¹⁹ cm^− 3, respectively. It was found that a peripheral surface-state current dominates the reverse leakage current in an n⁺/p junction diode. The protection of junction surfaces from plasma damage during the SiO₂ deposition was essential to achieve high-quality source/drain junctions. The surface passivation with a GeO₂ interlayer was harmful to an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) because of an increase in a surface leakage current due to inversion carriers. For a p-channel MOSFET, on the other hand, the GeO₂ interlayer plays a role in decreasing the surface leakage current.     

The effect of metallization contact resistance on the measurement of the field effect mobility of long-channel unannealed amorphous In-Zn-O thin film transistors

The effect of contact resistance on the measurement of the field effect mobility of compositionally homogeneous channel indium zinc oxide (IZO)/IZO metallization thin film transistors (TFTs) is reported. The TFTs studied in this work operate in depletion mode as n-channel field effect devices with a field effect mobility calculated in the linear regime (μ_FE) of 20 ± 1.9 cm²/Vs and similar of 18 ± 1.3 cm²/Vs when calculated in the saturation regime (μ_FE^sat). These values, however, significantly underestimate the channel mobility since a large part of the applied drain voltage is dropped across the source/drain contact interface. The transmission line method was employed to characterize the contact resistance and it was found that the conducting-IZO/semiconducting-IZO channel contact is highly resistive (specific contact resistance, ρ_C > 100 Ωcm²) and, further, this contact resistance is modulated with applied gate voltage. Accounting for the contact resistance (which is large and modulated by gate voltage), the corrected μ_FE is shown to be 39 ± 2.6 cm²/Vs which is consistent with Hall mobility measurements of high carrier density IZO.     

The effects of low temperature buffer layer on the growth of pure Ge on Si(001)

We investigated the effects of low temperature (LT) Ge buffer layers on the two-step Ge growth by varying the thickness of buffer layers. Whereas the two-step Ge layers using thin (< 40 nm) Ge buffer layers were roughened due to the formation of SiGe alloy, pure and flat Ge layers were grown by using thick (> 50 nm) LT Ge buffer layers. The lowest threading dislocation density of 1.2 × 10⁶ cm⁻² was obtained when 80-nm-thick LT Ge buffer layer was used. We concluded that the minimum thickness of buffer layer was required to grow uniform two-step Ge layers on Si and its quality was subject to the thickness of buffer layer.     

Electron energy loss spectroscopy study of the effect of low-energy Ar-ion bombardment on the surface structure and composition of Pt80Co20 (1 1 1) alloy

Electron energy loss spectroscopy has been employed for investigation of the effect of 600 eV Ar⁺-ion irradiation in the dose range 7×10¹⁶-4×10¹⁷ ions/cm² on the atomic structure and surface composition of alloy Pt₈₀Co₂₀(1 1 1). A method of the layer-by-layer reconstruction of the lattice interplanar distance changes based on the analysis of the plasmon spectra excitation was proposed. The ion bombardment was shown to result in a non-monotonic variation of the lattice interplanar distance due to formation of the stable defects, with the topmost layer being in the state of compression. Using the ionization energy loss spectra, a layer-by-layer concentration profile of the alloy components was reconstructed for different doses of ion irradiation of the surface. The Ar⁺-ion bombardment of the alloy was found to result in the preferential sputtering of Co and in the enrichment of the near-surface region by Pt atoms with formation of an altered layer, which is characterized by a non-monotonic concentration profile dependent on the irradiation dose. The results obtained are discussed in the framework of the models of preferential sputtering and radiation-induced segregation.     

Epitaxy of In0.01Ga0.99As on Ge/offcut Si (001) virtual substrate

In_0.01Ga_0.99As thin films free of anti-phase domains were grown on 7° offcut Si (001) substrates using Ge as buffer layers. The Ge layers were grown by ultrahigh vacuum chemical vapor deposition using ‘low/high temperature’ two-step strategy, while the In_0.01Ga_0.99As layers were grown by metal-organic chemical vapor deposition. The etch-pit counting, cross-section and plane-view transmission electron microscopy, room temperature photoluminescence measurements are performed to study the dependence of In_0.01Ga_0.99As quality on the thickness of Ge buffer. The threading dislocation density of Ge layer was found to be inversely proportional to the square root of its thickness. The threading dislocation density of In_0.01Ga_0.99As on 300 nm thick Ge/offcut Si was about 4 × 10⁸ cm^− 2. Higher quality In_0.01Ga_0.99As can be obtained on thicker Ge/offcut Si virtual substrate. We found that the threading dislocations acted as non-radiative recombination centers and deteriorated the luminescence of In_0.01Ga_0.99As remarkably. Secondary ion mass spectrometry measurement indicated as low as 10¹⁶ cm^− 3 Ge unintended doping in In_0.01Ga_0.99As.     

Electrical conductivity and Hall mobility in p-type TlGaSe2 crystals

Systematic dark electrical conductivity and Hall mobility measurements have been carried out in the temperature range of 200-350 K on p-type TlGaSe₂ crystals. The analysis of the temperature-dependent electrical conductivity and carrier concentration reveals the extrinsic type of conduction with an acceptor impurity level located at 0.33 eV, and donor and acceptor concentrations of 9.0×10¹⁵ and 1.3×10¹⁶ cm⁻³, respectively. A hole and electron effective masses of 0.520m₀ and 0.325m₀, respectively, with a donor to acceptor compensating ratio of 0.69 are also being identified. The Hall mobility is found to be limited by the hole-phonon short-range interactions scattering with a hole-phonon coupling constant of 0.17.     

Zinc oxide thin film transistors using MgO-Bi1.5Zn1.0Nb1.5O7 composite gate insulator on glass substrate

We report on high mobility ZnO thin film transistors (TFTs) (< 5 V), utilizing a room temperature grown MgO-Bi_1.5Zn_1.0Nb_1.5O₇ (BZN) composite gate insulator on a glass substrate. 30 mol% MgO added BZN composite gate insulators exhibited greatly enhanced leakage current characteristics (~< 2 × 10^− 8 A/cm² at 0.3 MV/cm) due to the high breakdown strength of MgO, while retaining an appropriate high-k dielectric constant of 32. The ZnO-TFTs with MgO-BZN composite gate insulators showed a high field-effect mobility of 37.2 cm²/Vs, a reasonable on-off ratio of 1.54 × 10⁵, a subthreshold swing of 460 mV/dec, and a low threshold voltage of 1.7 V.     

Monolithic integration of III-V optical interconnects on Si using SiGe virtual substrates

Working optical links epitaxially grown by atmospheric MOCVD and fabricated on Si via SiGe virtual substrates are demonstrated for the first time. The SiGe virtual substrates are graded from Si substrates to 100% Ge. Because of the 0.07% lattice mismatch between GaAs and Ge, high-quality GaAs-based thin films with threading dislocation densities <3×10⁶ cm^–2 were realized. The optical link consists of a GaAs PIN-LED and a GaAs PIN detector diode. A vertical-coupling scheme was utilized to couple devices with a Al_0.15Ga_0.85As waveguide. Waveguides of varying length, Y-junctions, and bends were fabricated. The straight waveguides exhibited loss of approximately 144 dB cm^–1.An erratum to this article can be found at     

High-performance ZnO thin film transistors with sputtering SiO2/Ta2O5/SiO2 multilayer gate dielectric

A high-performance ZnO thin film transistor （ZnO-TFT） with SiO₂/Ta₂O₅/SiO₂ (STS) multilayer gate insulator is fabricated by sputtering at room temperature. Compared to ZnO-TFTs with sputtering SiO₂ gate insulator, its electrical characteristics are significantly improved, such as the field effect mobility enhanced from 11.2 to 52.4 cm²/V s, threshold voltage decreased from 4.2 to 2 V, and sub-threshold swing improved from 0.61 to 0.28 V/dec. The improvements are attributed to the high gate capacitance (from 50 to 150 nF/cm²) as well as nice surface morphology by using dielectric with high～k Ta₂O₅ sandwiched by SiO₂ layers. The capacitance-voltage characteristic of a metal-insulator-semiconductor capacitor with the structure of Indium Tin Oxide/STS/ZnO/Al was investigated and the trap charges at the interface or bulk is evaluated to be 2.24 × 10¹² cm⁻². From the slope of C⁻² versus gate voltage, the doping density N_D of ZnO is estimated to be 1.49 × 10¹⁶ cm⁻³.