An Investigation into III–V Compounds to Reach 20% Efficiency with Minimum Cell Thickness in Ultrathin-Film Solar Cells

III–V single-junction solar cells have already achieved very high efficiency levels. However, their use in terrestrial applications is limited by the high fabrication cost. High-efficiency, ultrathin-film solar cells can effectively solve this problem, as their material requirement is minimum. This work presents a comparison among several III–V compounds that have high optical absorption capability as well as optimum bandgap (around 1.4 eV) for use as solar cell absorbers. The aim is to observe and compare the ability of these materials to reach a target efficiency level of 20% with minimum possible cell thickness. The solar cell considered has an n-type ZnSe window layer, an n-type Al_0.1Ga_0.9As emitter layer, and a p-type Ga_0.5In_0.5P back surface field (BSF) layer. Ge is used as the substrate. In the initial design, a p-type InP base was sandwiched between the emitter and the BSF layer, and the design parameters for the device were optimized by analyzing the simulation outcomes with ADEPT/F, a one-dimensional (1D) simulation tool. Then, the minimum cell thickness that achieves 20% efficiency was determined by observing the efficiency variation with cell thickness. Afterwards, the base material was changed to a few other selected III–V compounds, and for each case, the minimum cell thickness was determined in a similar manner. Finally, these cell thickness values were compared and analyzed to identify more effective base layer materials for III–V single-junction solar cells.     

Investigation of alternative window materials for GaAs solar cells

The optimum window material for surface passivation of GaAs solar cells is investigated using theoretical analysis of optical losses due to window bandgap energy and thickness. A simplified expression is developed to calculate the effective surface recombination velocity in terms of lattice mismatch between the window layer and GaAs, which suggests using a window material with and indirect bandgap energy greater than 2.0 eV, a thickness of less than 0.05 μm, and a lattice mismatch of less than 0.05%. Experimental GaAs solar cells were fabricated and quantum efficiency measurements were made using no window (bare GaAs), Al_0.7Ga_0.3As, Na₂S, and ZnSe/Na₂S windows. The Al_0.7Ga_0.3As and Na₂S windows are shown to passivate the GaAs surface and reduce the surface recombination velocity to less than 10⁵ cm/s, while the ZnSe encapsulating layer was used to permanently maintain the temporary surface passivation effects from Na₂S     

Local thickness and composition analysis of TEM lamellae in the FIB

High-resolution TEM image quality is greatly impacted by the thickness of the TEM sample (lamella) and the presence of any surface damage layer created during FIB–SEM sample preparation. Here we present a new technique that enables measurement of the local thickness and composition of TEM lamellae and discuss its application to the failure analysis of semiconductor devices. The local thickness in different device regions is accurately measured based on the X-ray emission excited by the electron beam in the FIB–SEM. Examples using this method to guide FIB–SEM preparation of high quality lamellae and to characterise redeposition are shown for Si and III–V semiconductor devices.     

胶层厚度对多点支撑光窗面形的影响

以某型战斗机光雷保护罩采用的多点支撑光窗为研究对象,建立胶层连接的多点边缘支撑结构模型,通过仿真分析胶层厚度对多点边缘支撑光窗面型的影响。建立“压块-胶层-光窗”有限元分析模型,在结构航向过载、航向随机振动、高低温冲击情况下,对不同胶层厚度仿真结果数据处理,分析胶层厚度对光窗面形变形的影响。结果可知:胶层在0.1~0.5 mm范围内,光窗表面PV值与RMS值,在过载冲击与随机振动仿真试验中,随着胶层厚度的增加呈现先减小后增加的趋势;在温度冲击仿真中,呈现逐渐减小的趋势。     

用于非破坏性读出铁电存储器的MFIS结构的机理研究

分析了 MFIS FET的工作机理以及影响 MFIS电容的存储窗口特性的因素 ,提出用存储窗口与铁电薄膜正、负矫顽电压的差值来评价存储窗口特性 ,制备了 Au/Cr/PZT/Zr O2 /Si的 MFIS结构并研究了其存储窗口特性 ,存储窗口随 Zr O2 的厚度变化呈现一个极大值 ,甚至会出现 C-V曲线方向的变化 ,而 PZT薄膜的厚度增大会导致窗口增大 ,这是由于界面效应以及在铁电层和介质阻挡层上电压分配关系的不同而造成的 ,这一结果与前面的分析很好地吻合。当 Zr O2 和 PZT的厚度分别为 3 0 nm和 2 5 0 nm、扫描电压从 -5 V到 +5 V变化时 ,存储窗口大小为 2 .5 V,与相应的铁电薄膜的正、负矫顽电压的差值的比为 0 .8。     

Impact of the Cd2+ treatment on the electrical properties of Cu2ZnSnSe4 and Cu(In,Ga)Se2 solar cells

The present contribution aims at determining the impact of modifying the properties of the absorber/buffer layer interface on the electrical performance of Cu₂ZnSnSe₄ (CZTSe) thin‐film solar cells, by using a Cd²⁺ partial electrolyte (Cd PE) treatment of the absorber before the buffer layer deposition. In this work, CZTSe/CdS solar cells with and without Cd PE treatment were compared with their respective Cu(In,Ga)Se₂ (CIGSe)/CdS references. The Cd PE treatment was performed in a chemical bath for 7 min at 70 °C using a basic solution of cadmium acetate. X‐ray photoemission spectroscopy measurements have revealed the presence of Cd at the absorber surface after the treatment. The solar cells were characterized using current density–voltage (J–V), external quantum efficiency, and drive‐level capacitance profiling measurements. For the CZTSe‐based devices, the fill factor increased from 57.7% to 64.0% when using the Cd PE treatment, leading to the improvement of the efficiency (η) from 8.3% to 9.0% for the best solar cells. Similar observations were made on the CIGSe solar cell reference. This effect comes from a considerable reduction of the series resistance (R_S) of the dark and light J–V, as determined using the one‐diode model. The crossover effect between dark and light J–V curves is also significantly reduced by Cd PE treatment. Copyright © 2015 John Wiley & Sons, Ltd.     

SET/RESET properties dependence of phase-change memory cell on thickness of phase-change layer

The thermal properties of a phase-change random access memory (PCRAM) cell are dominated by the phase-change recording material. The SET/RESET resistances, the minimum width of the SET/RESET pulse, the threshold voltage and the maximum temperature of PCRAM cells are impacted by the thickness of the phase-change layer. In this paper, a PCRAM cell with different Ge-Sb-Te phase-change layer thickness are fabricated, and the electrical properties of the PCRAM cells are tested. The SET/RESET properties dependence of PCRAM cells on the thickness of the phase-change layer is investigated and compared for the low-power consumption of PCRAM.     

Top‐Down Fabrication of High Quality III–V Nanostructures by Monolayer Controlled Sculpting and Simultaneous Passivation

In the fabrication of III–V semiconductor nanostructures for electronic and optoelectronic devices, techniques that are capable of removing material with monolayer precision are as important as material growth to achieve best device performances. A robust chemical treatment is demonstrated using sulfur (S)‐oleylamine (OA) solution, which etches layer by layer in an inverse epitaxial fashion and simultaneously passivates the surface. The application of this process to push the limits of top‐down nanofabrication is demonstrated by the realization of InP‐based high optical quality nanowire arrays, with aspect ratios more than 50, and nanostructures with new topologies. The findings are relevant for other III–V semiconductors and have potential applications in III–V device technologies.     

可折叠OLED屏幕的弯折应力仿真

柔性OLED屏幕在弯折的过程中,容易出现器件损伤、胶层剥离等现象。调整显示层的应力中性层位置和光学透明胶(OCA)胶层的应变是解决该问题的主要途径。本文通过建立柔性OLED屏幕的弯折仿真模型,分析了不同堆叠结构、保护盖板刚度、OCA胶层厚度、背板厚度和弯折半径对弯折后显示层应力中性层位置和OCA胶层应变的影响。结果表明,不同堆叠结构对显示层的应力中性层位置有很大影响,保护盖板刚度与OCA胶层厚度均对显示层的应力中性层位置无影响,背板厚度的增大使显示层应力中性层位置向下移动,弯折半径增大使结构应力下降,保护盖板刚度降低、OCA胶层厚度增大、背板厚度减小均对OCA胶层应变降低有利。仿真结果为柔性OLED的屏幕结构设计、材料选用以及解决弯折过程中出现的力学问题提供了参考。     

NEA光电阴极的表面模型

回顾了NEA光电阴极不同的表面模型，对异质结模型、偶极子模型和铯的弱核力效应进行了重点介绍。异质结模可以成功解释P型GaAs和（Cs,O）激活层之间界面势垒的存在，但这种具有体效应的异质结无法与（Cs，O）层的厚度相统一；偶极子模型认为在阴极表面形成的偶极层导致了逸出功的下降，其双偶极层模型能较好地预测和解释最佳的（Cs，O）激活层厚度，但不同的双偶极层模型对于氧在表面层存在的化学形态存在争议；铯的弱核力场效应认为铯表面层的弱核力场及氧的离化作用是界面势垒和负电子亲和势的形成原因，但它所认为的逸出功降低与基底材料无关还需进一步验证。     

Two-dimensional numerical analysis of the narrow gate effect in MOSFET

Lateral variation of the local threshold voltage causes non-linearity in the drain conductance-gate voltage characteristics, resulting in a nonunique external threshold voltage which varies with gate voltage. Using a 16-bit minicomputer, a two-dimensional (2-D) finite-difference program for narrow gate MOSFET (NAROMOS), and an accurate and efficient new finite-difference boundary equation at the oxide-semiconductor interface, computations are carried out for the external threshold voltage and a measurable electrical channel width as a function of the applied dc gate and substrate voltages. The depletion approximation is employed in order to compare the 2-D results with the 1-D analytical solution of the depletion model. Computed curves are presented for the lateral variations of the depletion layer thickness, surface potential, normal surface electric field, local as well as external threshold voltages, and electrical channel width as a function of the device structure, material parameters, and bias voltages. Based on the 2-D results and device physics, an analytical approximation of the threshold voltage versus the gate width, simple enough for CAD of VLSI, is derived whose parameters may be determined from either a 2-D computation or experimental measurements on one test device of a known gate width. The computed increase of the external threshold voltage with decreasing gate width compares well with published experimental data.     

Silicon-on-insulator nanotransistors with two independent gates

The results of numerical simulation of electrical characteristics of silicon-on-insulator MOSFET nanotransistors with two independent gates are reported. The cases of grounded and floating bases with the surface recombination of charge carriers either disregarded or taken into account are considered. It is shown that, at specified design parameters (gate length 50–100 nm, thickness of silicon layer 25–50 nm), one can vary the transistor’s threshold voltage by 0.45 V, reduce the transistor current in the off state by seven orders of magnitude, and decrease the subthreshold slope of the gate characteristics to 60 mV/decade by varying the voltage applied to the second gate. Suppression of the short-channel effects in the transistors under consideration depends on a number of parameters (listed in order of decreasing effect): the gate material, the lifetime of charge carriers (for floating or grounded base), the thickness of the top silicon layer, the voltage applied to the additional gate, and the channel length.     

High efficiency all‐GaAs solar cell

The reduction of surface recombination in GaAs solar cells is known to be a major concern for photovoltaic cells designers. A common technique used to reduce this effect is to cover the GaAs surface with a wide band gap window layer, therefore the creation of a heterojunction. To avoid a heterojunction with its inconveniences; interface surface states, poor photon absorption in addition to the technological exigencies, one can use an all‐GaAs solar cell. In this type of structure, a thin highly doped layer is created at the surface known as a front surface field (FSF). The main role of an FSF layer is to reduce the effect of front surface recombination and the enhancement of light‐generated free carriers' collection. This is achieved by the drastic reduction of the effective recombination at the emitter upper boundary. In this work, a simple analytical model is used to simulate the influence of the FSF layer on GaAs solar cell parameters; photocurrent, open circuit voltage and energy conversion efficiency. The effects of the FSF layer doping density and its thickness on the cell performance are discussed by using computed results. Copyright © 2010 John Wiley & Sons, Ltd.     

激光参量对碳钢表面清洗质量的影响

为了研究激光工艺参量对碳钢表面锈蚀污染层清洗质量的影响规律,采用Nd:YAG准连续激光器对Q235钢板试样进行了激光除锈清洗试验,并观测了试样表面清洗质量.分析了激光清洗污染物烧蚀的工作机理,并试验研究了激光能量密度、扫描速率、扫描宽度、离焦量和重复频率等工艺参量对清洗质量的影响,在此基础上进行了正交试验;通过对激光清...     

纳米硅/晶体硅异质结电池的暗I-V特性和输运机制

采用HWCVD技术在P型CZ晶体硅衬底上制备了纳米硅／晶体硅异质结太阳电池,测量了晶体硅表面在不同氢处理时间下的异质结的暗I-V特性和相应的电池性能参数．室温下的正向暗I-V特性采用双二极管模型来拟合,可将0～1V的电压范围区分为4个区域：旁路电阻（0～0．15V）、非理想二极管2（0．15～0．3V）、理想二极管1（0．3～0．5V）和串联电阻（〉0．5V）．拟合结果表明,适当的氖处理时间（～30s）可有效降低非理想二极管的理想因子n2,即降低界面复合电流,表明具有好的界面特性．对于282～335K的暗I—V温度特性的研究表明,在0．15～0．3V的低电压范围,暗电流主要由耗尽区的复合电流提供,0．3～0．5V电压范围,对输运起主要作用的是隧穿过程,该过程可用通过界面陷阱能级的隧穿模型来解释．     

中国微米纳米学会－微型压电振动发电机谐振频率调节技术的研究

具有高能量密度的微型压电振动发电机可以无限、持续地为无线传感器网络提供能量。为了适应环境振源频率的变化,提高压电振动发电机的能量转换效率,采用理论建模和数值分析的方法,研究了旁路电容调节振动发电机固有频率的关键技术。建立压电电容与压电层杨氏模量的力学模型,分析压电电容对压电发电机固有频率的影响规律,提出了单晶片和双晶片压电梁的电容频率调节配置方案;分别研究厚度比、长度和宽度对开路、闭路刚度比及固有频率比的影响特性,对结构参数进行了优化配置。     

Side-emitting GaAs/AlGaAs SQW LEDs showing wide spectrum using shadow masked growth

Side-emitting LEDs are proposed showing a wide optical spectrum. The LEDs were fabricated using a special growth technique called shadow masked growth (SMG). The width of the window in the shadow mask was gradually changed along the LED stripe direction and therefore resulted in a continuous variation of the layer thickness. The combination with a quantum well active region results in a continuous variation in bandgap and emission wavelength. These different spectra add up at one side of the LED offering a broad spectrum. By decreasing the width of the window, starting from 100 mu m, GaAs/AlGaAs GRINSCH SQW LEDs have been realised with spectral widths up to 63 nm and very small spectral ripple.<>     

基于双结模型非理想太阳能电池伏安特性参数数值分析

提出了一种对于太阳电池光照条件和暗特性条件下对其伏安特性全段进行拟合提取参数的改进方法.对太阳电池J-V曲线进行分段, 提取每段的4个关键参数: 串联电阻(Rs)、并联电阻(Rsh)、品质因子(n)、反向饱和电流密度(J0).这种方法采用了双结电路模型法, 并以CdS/CdTe薄膜电池为例进行了光照下和暗特性分析, 得到了比单结电流模型更多的参数, 并且具有较高的拟合精度(误差<0.7%).     

金属雷电分流条对雷达罩电性能的影响分析

论文建立了天线罩分流条电磁传输研究模型,通过仿真和实验,对比分析了雷电分流条的电磁波传播特性,特别研究了中空十字型和十字型金属分流条的电磁波传输机理,以及金属分流条的材料、长度、宽度、厚度和电磁波不同入射方向对雷达罩电磁波传输性能的影响。研究结果表明:十字型金属雷电分流条对天线罩的电磁传输影响严重,而设计合理的中空十字金属分流条可以有效传输电磁波;另外,金属分流条的厚度和常用金属材料对电磁波传输影响不大,主要影响其导电能力和重量;在保证天线罩雷击安全的前提下,调整金属条长度可以使天线罩电性能达到最佳;金属条的宽度对电磁波传输性能影响明显,宽度越大,天线远场方向图主瓣增益越大;随着入射角的增大,方向图主瓣增益在减小,入射角超过30°时,雷电分流条对天线罩的电磁传输为负影响。     

熔覆层厚度对相控阵表面波聚焦特性的影响

超声表面波是检测激光熔覆层质量的重要手段,为提高检测分辨率,采用可达到声束聚焦效果的相控阵表面波对激光熔覆层进行检测。建立了单探头与相控阵表面波传播的有限元模型,基于Fermat原理研究超声波传播路径并分析了阵元延时特性,实现了相控阵表面波的聚焦和偏转,研究了熔覆层厚度对相控阵表面波聚焦特性的影响。结果表明,对于基体材料为铝,熔覆层材料为45#钢时,熔覆层厚度在2.5 mm内,聚焦点的能量随厚度增加而减小,如1 mm厚相对于0.2 mm厚的聚焦点能量减小了58.8%;当厚度大于2 mm时,聚焦点处能量变化不明显,表明超声相控阵表面波对薄的熔覆层具有较好的检测效果。