Efficient three‐dimensional parallel simulations of PHEMTs

An efficient 3D semiconductor device simulator is presented for a memory distributed multiprocessor environment using the drift–diffusion (D–D) approach for carrier transport. The current continuity equation and the Poisson equation, required to be solved iteratively in the D–D approach, are discretized using a finite element method (FEM) on an unstructured tetrahedral mesh. Parallel algorithms are employed to speed up the solution. The simulator has been applied to study a pseudomorphic high electron mobility transistor (PHEMT). We have carried out a careful calibration against experimental I–V characteristics of the 120 nm PHEMT achieving an excellent agreement. A simplification of the device buffer, which effectively reduces the mesh size, is investigated in order to speed up the simulations. The 3D device FEM simulator has achieved almost a linear parallel scalability for up to eight processors. Copyright © 2005 John Wiley & Sons, Ltd.     

3D Parallel Simulations of Fluctuation Effects in pHEMTs

The use of 3D simulations is essential in order to study the effects of fluctuations when devices are scaled to deep submicron dimensions. A 3D drift-diffusion device simulator has been developed to effectively simulate pseudomorphic high electron mobility transistors (pHEMTs) on a distributed memory multiprocessor computer. The drift-diffusion equations are discretized using a finite element method on an unstructured tetrahedral mesh. The obtained set of equations is solved in parallel on an arbitrary number of processors using the message-passing interface library. We have applied our simulator to a 120 nm pHEMT based on the Al_0.3Ga_0.7As/In_0.2Ga_0.8As interface and carried out a calibration to real experimental data.     

A parallel 3D semiconductor device simulator for gradual heterojunction bipolar transistors

In this paper, we present a parallel three‐dimensional semiconductor device simulator for gradual heterojunction bipolar transistor. This simulator uses the drift‐diffusion transport model. The Poisson equation and continuity equations were discretized using a finite element method (FEM) on an unstructured tetrahedral mesh. Fermi–Dirac statistics is considered in our model and a compact formulation is used that makes it easy to take into account other effects such as the non‐parabolic nature of the bands or the presence of various subbands in the conduction process. Domain decomposition methods were tested to solve the linear systems. We have applied this simulator to a gradual heterojunction bipolar transistor (HBT), and we present some measures of the parallel execution time for several solvers and some electrical results. This code has been implemented for distributed memory multicomputers, making use of the MPI message passing standard library and a parallel solver library. Copyright © 2002 John Wiley & Sons, Ltd.     

Fast 3D thermal simulation of power module packaging

This paper presents a thermal model that uses a Fourier series solution to the heat equation to carry out transient 3D thermal simulation of power device packaging. The development and implementation of this physics‐based method is described. The method is demonstrated on a stacked 3D multichip module. The required aspects of 3D heat conduction are captured successfully by the model. Compared with previous thermal models presented in literature, it is fast, accurate and can be easily integrated with an inverter circuit simulator to model realistic converter load cycles. Copyright © 2012 John Wiley & Sons, Ltd.     

Tetrahedral elements in self-consistent parallel 3D Monte Carlo simulations of MOSFETs

Novel thin-body architectures with complex geometry are becoming of large interest because they are expected to deliver the ITRS prescribed on-current when semiconductor transistors are scaled into nanometer dimensions. We report on the development of a 3D parallel Monte Carlo simulator coupled to a finite element solver for the Poisson equation in order to correctly describe the complex domains of advanced FinFET transistors. We study issues such as charge assignment, field calculation, treatment of contacts and parallelisation approach which have to be taken into account when using tetrahedral elements. The applicability of the simulator is demonstrated by modelling a 10 nm gate length double gate MOSFET with a body thickness of 6.1 nm.     

Statistical study of the effect of interface charge fluctuations in HEMTs using a 3D simulator

The intrinsic parameter fluctuations associated with the discreteness of charge and matter become an important factor when the semiconductor devices are scaled to nanometre dimensions. The interface charge in the recess regions of high electron mobility transistors (HEMTs) has a considerable effect on the overall device performance. We have employed a 3D parallel drift-diffusion device simulator to study the impact of interface charge fluctuations on the I-V characteristics of nanometre HEMTs. For this purpose, two devices have been analysed, a 120 nm gate length pseudomorphic HEMT with an In_0.2Ga_0.8As channel and a 50 nm gate length InP HEMT with an In_0.7Ga_0.3As channel.     

Study of self-heating effects in SOI and conventional MOSFETs with electro-thermal particle-based device simulator

In this paper we present a study of self-heating effects in nanoscale SOI (Silicon-On-Insulator) devices and conventional MOSFETs using an in-house electro-thermal particle-based device simulator. We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional (2D) and the three-dimensional version (3D) of the tool) and then we present a series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in SOI technology. Our simulation results for planar SOI devices (using 2D version of the tool) show that in the smallest devices considered, heat dissipation occurs in the contacts, not in the active channel region of the device. This is because of two factors: pronounced velocity overshoot effect and the smaller thermal resistance of the buried oxide layer. We propose methods in which heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. To simulate self heating in nanowire transistors, the 2D simulator was extended to three spatial dimensions. We study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel in nanowire transistors, the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel. Finally, we examine the importance of self-heating effects in conventional MOSFETs used for low-power applications. We find that the average temperature increase obtained with our simulator of about 10 K is almost identical to the value that has to be used in low-power circuit simulations.     

MMICs time‐domain electrical physical simulator adapted to the parallel computation

The programming method used to adapt an existing time‐domain electrical circuit simulator to the parallel computation is presented. The originality of the simulator results in the semiconductor device numerical physical modeling. Thus, the organization of the existing software, initially developed to be run on a monoprocessor sequential Unix workstation, is firstly detailed. Accounting for specifications at once regarding the effort necessary to modify the software, the wished simulator application field and the constraints resulting from the available computer, two levels of parallelization have been pointed out and implemented by means of the message passing interface parallel programming tool. As an illustration, some results concerning the simulation of a microwave monolithic integrated circuit (MMIC), especially a 2–40 GHz HEMT transistor cascode stage distributed amplifier, are presented. Circuits of increasing complexity have been considered. The evaluation of the sequential/parallel computation ratio demonstrates that significant gains can be expected from the parallel computation opening the way to analysis of the operation of MMICs of mean complexity by means of a numerical physical approach. Copyright © 2008 John Wiley & Sons, Ltd.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

Towards the global modeling of InGaAs-based pseudomorphic HEMTs

We utilize a 3D full-band Cellular Monte Car- lo (CMC) device simulator to model ultrashort gate length pseudomorphic high-electron-mobility transistors (p-HEMTs). We present the static dc device characteristics and rf response for gate lengths ranging from 10 nm to 50 nm. Preliminary passive results using 3D full-wave Maxwell solver are also presented to illustrate the usefulness of and insight that a future coupled full-band/full-wave simulator will provide in more accurately, modeling the high frequency performance of p-HEMTs.     

Fully 3D self-consistent quantum transport simulation of Double-gate and Tri-gate 10 nm FinFETs

We utilize a fully self-consistent 3D quantum mechanical simulator based on the Contact Block Reduction (CBR) method to investigate the effects of fin height and unintentional dopant on the device characteristics of a 10-nm FinFET device. The per-fin height off-current is found to be relatively insensitive to fin height while the corresponding per fin height on-current may significantly depend on fin height due to the stronger confinement with decreasing fin height. Also gate leakage is found to show similar behavior as device on-current with decreasing fin height. Tri-gate (TG) FinFET is found to show better performance compared to Double-gate (DG) FinFET, with the exception of gate leakage current. Simulation results show that an unintentional dopant within the channel can significantly alter device characteristics depending on its position and applied biases. In addition, the effects of unintentional dopant are found to be stronger at high drain bias than at low drain bias.     

Numerical analysis of abrupt heterojunction bipolar transistors

This paper presents a physical–mathematical model for abrupt heterojunction transistors and its solution using numerical methods with application to InP/InGaAs HBTs. The physical model is based on the combination of the drift–diffusion transport model in the bulk with thermionic emission and tunnelling transmission through the emitter–base interface. Fermi–Dirac statistics and bandgap narrowing distribution between the valence and conduction bands are considered in the model. A compact formulation is used that makes it easy to take into account other effects such as the non-parabolic nature of the bands or the presence of various subbands in the conduction process. The simulator has been implemented for distributed memory multicomputers, making use of the MPI message-passing standard library. In order to accelerate the solution process of the linear system, iterative methods with parallel incomplete factorization-based preconditioners have been used. © 1998 John Wiley & Sons, Ltd.     

Green's function approach for modeling of electrostatic effects in nanoscale fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistors

Exact solution of two‐dimensional (2D) Poisson's equation for fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistor is derived using three‐zone Green's function solution technique. Framework consists of consideration of source–drain junction curvature. 2D potential profile obtained forms the basis for estimation of threshold voltage. Temperature dependence of front surface potential distribution, back surface potential distribution and front‐gate threshold voltage are modeled using temperature sensitive parameters. Applying newly developed model, surface potential and threshold voltage sensitivities to gate oxide thickness have been comprehensively investigated. Device simulation is performed using ATLAS 2D (SILVACO, 4701 Patrick Henry Drive, Bldg. Santa Clara, CA 95054 USA) device simulator, and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data. Copyright © 2013 John Wiley & Sons, Ltd.     

Compact modeling and simulation of nanoscale fully depleted DG-SOI MOSFETS

A two dimensional analytical model for nanoscale fully depleted double gate SOI MOSFET is presented. Green??s function solution technique is adopted to solve the two dimensional Poisson??s equation using Dirichlet??s and Neumann??s boundary conditions at silicon-silicon di-oxide interface. Based on the derived 2D potential distribution, surface potential distributions in the Si film are analytically obtained. The calculated minimum surface potential is used to develop an analytic threshold voltage model. Simulation is done using ATLAS simulator for a 65?nm device and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data and other published results.     

Verification of 1D BJT numerical simulation and its application to mixed‐level device and circuit simulation

In this paper, we study on a 1D BJT model, which saves the memory size and computation time and verify that the characteristic of 1D BJT model is in good agreement with 2D BJT model. We use the equivalent circuit approach to simulate the BJT device. Poisson's equation and continuity equations for electron and hole are formulated into a subcircuit format suitable for general circuit simulator in the equivalent circuit approach. In order to solve the 2D device simulation, the simulation environment needs a powerful solver. So we use the band matrix solver to replace the full matrix solver. But the 2D BJT simulation still needs a large computation time, so we must develop the efficient 1D BJT model. In 1D BJT simulation, we have overcome the base boundary condition and verified that the base boundary conditions in 1D BJT model closely approach to that in 2D BJT model. Finally, we apply it to two applications and study the operation concepts of these applications. Copyright © 2002 John Wiley & Sons, Ltd.     

Modeling of FinFET: 3D MC Simulation Using FMM and Unintentional Doping Effects on Device Operation

Novel device concepts such as dual gate SOI, Ultra thin body SOI, FinFETs, etc., have emerged as a solution to the ultimate scaling limits of conventional bulk MOSFETs. These novel devices suppress some of the Short Channel Effects (SCE) efficiently, but at the same time more physics based modeling is required to investigate device operation. In this paper, we use semi-classical 3D Monte Carlo device simulator to investigate important issues in the operation of FinFETs. Fast Multipole Method (FMM) has been integrated with the EMC scheme to replace the time consuming Poisson equation solver. Effect of unintentional doping for different device dimensions has been investigated. Impurities at the source side of the channel have most significant impact on the device performance.     

数字实时仿真在控制和保护系统测试中的应用

HVDC和FACTS装置的控制和保护系统在投运前必须进行仿真测试,以验证系统性能.文中结合实际工程项目,详细阐述了数字实时仿真系统进行HVDC和FACTS装置控制和保护系统实时测试的原理和过程.在此基础上进一步阐述了数模混合实时仿真系统的结构和应用情况,同时提出了先进集成混合实时仿真系统的架构和原理.混合实时仿真系统可经济有效地扩大实时测试系统的规模.项目中装置投运后现场试验的结果验证了实时测试的准确性.     

Computational study of double-gate graphene nano-ribbon transistors

The ballistic performance of graphene nanoribbon (GNR) MOSFETs with different width of armchair GNRs is examined using a real-space quantum simulator based on the Non-equilibrium Green’s Function (NEGF) approach, self-consistently coupled to a 3D Poisson’s equation for electrostatics. GNR MOSFETs show promising device performance, in terms of low subthreshold swing and small drain-induced-barrier-lowing due to their excellent electrostatics and gate control (single monolayer). However, the quantum tunneling effects play an import role in the GNR device performance degradation for wider width GNR MOSFETs due to their reduced bandgap. At 2.2 nm width, the OFF current performance is completely dominated by tunneling currents, making the OFF-state of the device difficult to control.     

交直流大电网数模混合仿真系统的并行计算效率研究

国家电网仿真中心基于SGI Altix 4700超级计算机及全数字实时仿真软件Hypersim建立了交直流大电网数模混合实时仿真系统,Hypersim应用LDU分解算法求解节点电压方程,对网络进行分网并行计算,分析了影响仿真系统并行计算效率的因素。三华电网仿真结果表明,该仿真系统能够满足大电网实时仿真要求,具有较高的并行计算效率。     

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the “virtual cathode” concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson’s equation with suitable boundary conditions in both the strained-Si layer and relaxed Si_1?x Ge _x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.