一种基于FPGA的准单输入跳变序列生成器设计

本文针对一种准单输入跳变序列测试生成器的测试缺点,提出了一种改进的设计方案并且利用EDA技术在FPGA芯片上进行了设计实现.     

基于低功耗及加权优化的BIST测试生成器设计实现

测试生成器TPG（Tesl Panern Generation）的构造是BIST（Built—In Self-Test）测试策略的重要组成部分。文章结合加权伪随机测试原理及低功耗设计技术，提出了一种基于低功耗及加权优化的BIST测试生成器设计方案。它根据被测电路CUT（Circuit Under Test）各主输入端口权值构造TPG，在对测试序列优化的同时达到降低功耗的目的。仿真结果验证了该方案的可行性。     

基于FPGA的Lorenz混沌序列的设计及统计测试

硬件加密及混沌算法的应用在信息安全领域中有重要的意义.这里以一种实际应用中常用的Lorenz混沌系统为例,介绍了利用FPGA技术实现该混沌序列的一种物理生成方法,并介绍了衡量此随机比特生成器质量的统计测试方法,这不同于以往的普通序列测试.通过统计测试实验表明,此随机比特生成器所生成的四个序列中x序列的统计特性没有其它三个序列好,在实际运用中应加以注意.可见统计测试在随机比特生成器的质量验证中有着很为必要的作用.     

折叠控制器的低功耗改进设计

文章提出了一种硬件开销小的降低测试功耗的折叠控制器设计方案,该设计方案在原有折叠控制器的基础上只需对其中的折叠索引计数器进行改进设计,从而得到伪单输入跳变的测试向量集,达到降低待测电路功耗的目的。     

一种新的低功耗BIST测试生成器设计

文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的BIST测试生成器设计方案,该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑电路,对LFSR的输出和时钟进行调整,从而得到了准单输入跳变的测试向量集,使得待测电路的平均功耗大大降低.由于该设计方案比其它LPTPG方案的面积开销小,从而具有更好的使用价值.     

低功耗测试序列生成电路的建模及分析

为了解决深亚微米、SOC和低功耗电路中的测试问题,低功耗测试序列RSIC序列的生成方法得以研究和发展.文章提出关于RSIC序列生成电路的建模和分析理论.其研究特色是抽象出此类复杂电路固有特性的通用模型,建立一套简洁、准确的数学描述和分析方法,论证了此类电路的一系列特性,并通过片外测试的模拟结果来验证RSIC序列的低功耗.该研究结果为RSIC序列研究和应用提供了强有力的理论基础和分析方法.     

基于折叠集的混合模式BIST的低功耗设计

文章提出了一种基于折叠集的混合模式BIST低功耗设计方案,该设计方案通过对混合模式BIST的优化设计,得到伪单输入跳变的测试向量集,从而达到降低待测电路功耗的目的.     

低功耗测试矢量生成技术的研究

在集成电路内建自测试的过程中,电路的测试功耗通常显著高于正常模式产生的功耗,因此低功耗内建自测试技术已成为当前的一个研究热点。为了减少被测电路内部节点的开关翻转活动率,研究了一种随机单输入跳变（Random Single Input Change,RSIC）测试向量生成器的设计方案,利用VHDL语言描述了内建自测试结构中的测试向量生成模块,进行了计算机模拟仿真并用FPGA（EP1C6Q240C8）加以硬件实现。实验结果证实了这种内建自测试原理电路的正确性和有效性。     

基于FPGA的AGWN信号生成器

提出一种新的基于FPGA的高斯白噪声生成器的设计和实现方法,给出设计的总体框图和分模块设计中的一些要点,阐述了主要部分的原理和电路实现方法。这种高斯噪声生成器与传统数字电路所组成的噪声生成器相比,通过利用QuartusⅡ中的一些既有功能电路（PLL）,大大降低了设计的难度,提高了电路调试的灵活性,可用于多种环境下的通信系统性能分析与测试。     

CLA加法器混合式BIST方案

本文以先行进行加法器为例,将确定性测试方法与伪随机测试方法相结合,提出了实现内建自测试电路中测试生成器的、在测试昨测试电路硬件开锁之间取得折衷的几种方案。最后,比较并分析了所得结果。     

一种基于扫描结构的混合模式BIST的低功耗设计

针对扫描结构混合模式BIST的特点,文章提出了一种利用双模式LFSR和新型折叠控制器相结合的方法来对基于扫描结构的混合模式BIST电路进行低功耗优化设计,从而达到降低待测电路功耗的目的.     

一种新型低峰值功耗的BIST设计研究

随着手持设备的兴起和芯片对晶片测试的要求越来越高,内建自测试的功耗问题引起了越来越多人的关注。文章对目前内建自测试的可测性设计技术进行了分析,并提出了折叠种子优化降低节点峰值功耗的模型,通过调整种子结构和测试向量的相关性的办法来避免过高的SoC测试峰值功耗。采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用,使得测试时测试向量的输入跳变显著降低,从而大幅度降低节点的峰值功耗。实验结果表明,该方案可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

基于LFSR优化的BIST低功耗设计

在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗。在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求。     

SOC基于LFSR的混合模式测试

随着集成电路深亚微米制造技术和设计技术迅速发展,系统芯片(SOC)作为一种解决方案得到了越来越广泛的应用。SOC的测试中,内建自测试(Built.In Self-Test,BIST)成为人们研究的热点。文中对SOC的设计特点及其BIST中的混合模式测试进行了探讨。     

On chip testing data converters using static parameters

In this paper, built-in self-test (BIST) approach has been applied to test digital-to-analog (D/A) and analog-to-digital (A/D) converters. Offset, gain, integral nonlinearity (INL), and differential nonlinearity (DNL) errors and monotonicity are tested without using mixed-mode or logic test equipment. An off-line calibrating technique has been used to insure the accuracy of BIST circuitry and to reduce area overhead by avoiding the use of high quality analog blocks. The proposed BIST structure presents a compromise between test cost, area overhead, and test time. By a minor modification the test structure would be able to localize the fail situation. The same approach may be used to construct a fast low cost off-chip D/A converter tester. The BIST circuitry has been designed and evaluated using complementary metal-oxide-semiconductor (CMOS) 1.2 μm technology     

On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level

Test power requirements for complex components are becoming stringent. The purpose of this paper is to reuse a recently proposed RT (Register Transfer) Level test preparation methodology to drive innovative Low-Energy (LE)/Low-Power (LP) BIST solutions for digital SoC (System on a Chip) embedded cores. RTL test generation is carried out through the definition of a reduced set of partially specified input vectors (masks), leading to a high correlation between multiple detection of RTL faults and single detection of likely physical defects. The methodology is referred as masked-based BIST, or m-BIST. BIST quality is evaluated considering three attributes: test effectiveness (TE), test length (TL) and test power (TP). LE BIST sessions are defined as short test sequences leading to high values of RT-level IFMB metrics and low-level Defects Coverage (DC). The energy and power of the BIST sessions, with and without mask forcing, is computed. It is shown that, by forcing vectors with the RTL masks, short BIST sessions, with low energy and with a comparable (or smaller) average power consumption, as compared to pseudo-random test, are derived. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and modules of the CMUDSP and TORCH ITC'99 benchmark circuits.     

Fully Programmable Memory BIST for Commodity DRAMs

To accomplish a high‐speed test on low‐speed automatic test equipment (ATE), a new instruction‐based fully programmable memory built‐in self‐test (BIST) is proposed. The proposed memory BIST generates a high‐speed internal clock signal by multiplying an external low‐speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on‐the‐fly to perform complicated and hard‐to‐implement functions, such as loop operations and refresh‐interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.     

A Built-in-Self-Test Σ-Δ ADC Prototype

This paper presents a built-in-self-test (BIST) Σ-Δ ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability Σ-Δ modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard ??6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.     

Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.