Bit-Level systolic architectures for high performance IIR filtering

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware.This paper is a revised and extended version of a paper by the same authors presented at the second International Conference on Systolic Arrays, San Diego, May 1988 [1].     

VLSI computing architectures for Haar transform

The Haar transform is very useful in many signal and image processing applications where real-time implementation is essential. Three VLSI computing architectures are proposed for fast implementation of the Haar transform. Comparisons on the advantages and disadvantages of the proposed architectures are also presented.<>     

Tree-based special-purpose Array architectures for neural computing

A massively parallel architecture called the mesh-of-appendixed-trees (MAT) is shown to be suitable for processing artificial neural networks (ANNs). Both the recall and the learning phases of the multilayer feedforward with backpropagation ANN model are considered. The MAT structure is refined to produce two special-purpose array processors; FMAT1 and FMAT2, for efficient ANN computation. This refinement tends to reduce circuit area and increase hardware utilization. FMAT1 is a simple structure suitable for the recall phase. FMAT2 requires little extra hardware but supports learning as well. A major characteristic of the proposed neurocomputers is high performance. It takesO (logN) time to process a neural network withN neurons in its largest layer. Our proposed architecture is shown to provide the best number of connections per unit time when compared to several major techniques in the literature. Another important feature of our approach is its ability to pipeline more than one input pattern which further improves the performance.The authors acknowledge the support of the NSF and State of Louisiana grant NSF/LEQSF (1992–96)-ADP-04.     

A high performance architecture for computing the time-frequency spectrum

To solve the problem of detecting and displaying the changes in the spectra of nonstationary signals, there are two possible approaches. Either one uses the same estimators as for the stationary signals, but one approach uses shorter-length data blocks during which the signal is assumed to be stationary, and the other one uses the same length data and applies a time-varying spectrum estimator that accounts for the nonstationarity. A time-varying spectrum estimator called a time-varying correlogram (TVC) is a well-known estimator of the time-frequency spectrum of a nonstationary signal. In this paper, a high performance VLSI architecture for computing TVC is proposed.     

Modular VLSI architectures for computing the arithmetic Fouriertransform

Modular, area-efficient VLSI architectures for computing the arithmetic Fourier transform (AFT) are proposed. By suitable design of PEs and I/O sequencing, nonuniform data dependencies in the AFT computation which require nonequidistant inputs and assignment of Mobius function values are resolved. The proposed design employs 2N+1 PEs to compute 2N+1 Fourier coefficients. Each PE has an adder and a fixed amount of local storage, and one PE has a multiplier. I/O with the host is performed using a fixed number of channels. This results in simple PE organization, compared with those needed in known DFT/FFT architectures. The design achieves O(N) speedup. It uses significantly fewer PEs than designs in the literature and supports real-time applications by allowing continuous sequential input. It can be extended to achieve linear speedup in a fixed size array with 2p+1 PEs, 1⩽p⩽N     

一种高性能并行计算架构的FPGA实现

针对传统的现场可编程门阵列（Field Programmable Gate Array,FPGA）开发方法效率低、不能充分利用芯片逻辑资源等问题,提出了一种高性能并行计算架构。设计了统一的软件、硬件编程模型,并提供FPGA操作系统层级的支持,将部分可重构技术应用于硬件线程的开发,使该架构具备资源管理和复用的能力。同时还设计了软件、硬件协同开发的流程。在开发板ZC702上进行了设计验证,评估了架构的额外资源消耗情况,并以排序算法为例展示了该架构多线程设计的灵活性。     

Low-power equalizer architectures for high speed modems

In many DSP-based high-speed modem applications, such as broadband modems for high-speed Internet access to the home or gigabit Ethernet transceivers, channel equalization requires processing power so high that power consumption and clock speed become major design challenges. This article describes techniques to implement low-cost adaptive equalizers for ASIC implementations of broadband modems. Power consumption can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techniques. The derivation of a hybrid FIR filter structure is given that enables the designer to adjust both the speed and power consumption to suit an application. Furthermore, the architecture can be made programmable to target multiple applications in one piece of silicon while maintaining or even improving the efficiency of the architecture. Run-time techniques are shown that can minimize the power consumption for a given application or operating environment. In all cases, the power reduction techniques are supported by simulations and measurements made on a test integrated circuit     

基于Linux的高性能集群的构建和性能优化

提出并实现了一种并行计算集群搭建的方案,采用国际通用的HPL标准进行浮点运算性能的测试。在优化集群高性能运算性能的方面,对传统基于经验的穷举办法进行优化,提出一种基于参数影响因子排序的优化方案,有效地减少了穷举法盲目试验的时间。另外次算法还具有一定的开放性,以往的经验数据可以得到有效利用。     

Derivation of Markov models for effectiveness analysis of adaptable software architectures for mobile computing

Adaptable software architectures (SA) have been suggested as a viable solution for the design of distributed applications that operate in a mobile computing environment to cope with the high heterogeneity and variability of this environment. Mobile code techniques can be used to implement this kind of SA since they allow us to dynamically modify the load of the hosting nodes and the internode traffic to adapt to the resources available in the nodes and to the condition of the (often wireless) network link. However, moving code among nodes has a cost (e.g., in terms of network traffic and consumed energy for mobile nodes), so designing an adaptable SA based on mobile code techniques requires a careful analysis to determine its effectiveness from the early design stages. In this respect, our main contribution consists of a methodology, called ASAP (adaptable software architectures performance), to automatically derive, starting from a design model of a mobility-based SA, a Markov model whose solution provides insights about the most effective adaptation strategy based on code mobility in a given execution environment. We assume that the SA model is expressed using the Unified Modeling Language (UML) because of its widespread use in software design, also suggesting some extension to this formalism to better express the "mobility structure" of the application, i.e., which are the mobile components, and the possible targets of their movement.     

Crosslink architectures for a multiple satellite system

Several candidate crosslink communications architectures are described for a packet-switched, low-altitude, multiple satellite system (MSS). One architecture represents a frequency-division approach, in which a cellular concept is combined with dynamic time-domain allocation within a cell. A second architecture uses an unsynchronized space-time division approach consisting of directional antennas and random accessing. A third architecture uses toroiclal antennas with unsynchronized random accessing. The recommended architecture uses a synchronized space-time division approach, consisting of directional antennas and contention-based pair-wise scheduling. This architecture, called PRS (Pseudo-random Scheduling) is found to have significantly reduced power and bandwidth requirements relative to the other approaches.     

平台级FPGA满足高性能系统集成的需求

一、高性能电子系统的性能需求 信号处理是信息处理的基础,包括从不同环境中提取信息的各种方法。现代信号处理主要考虑采用数字技术,复杂的高性能数字信号处理系统通常是由执行基本数字信号处理运算的子系统综合而成的。     

Cooperative communication system for high performance using ambient signals

This paper proposes the Internet connectivity of RF-powered devices in the backscatter system. The RF-powered devices do not use a battery and charge energy by harvesting from ambient RF signals of TV, a cellular phone and Wi-Fi devices. The Internet connectivity of the RF-powered devices in the backscatter system is very useful in Internet of things technology because the RF-powered devices which are called to a tag have a small size by the harvesting from ambient RF signals without a battery. This paper proposes a method improving the communication performance of the Wi-Fi backscatter system by applying the cooperative communication scheme.

     

COD: alternative architectures for high speed packet switching

Architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to utilize advances in photonic technology to enable higher speeds. The authors introduce cascaded optical delay line (COD) architectures. The COD architectures utilize an extremely simple distributed electronic control algorithm to configure the states of 2×2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessary. The simplicity of the architectures may also make them suitable for “lightweight” all-electronic implementations. For optical implementations, the number of 2×2 photonic switches used is a significant factor determining cost. The authors present a “baseline” architecture for a 2×2 buffered packet switch that is work conserving and has the first-in, first-out (FIFO) property. If the arrival processes are independent and without memory, the maximum utilization factor is ρ, and the maximum acceptable packet loss probability is ϵ, then the required number of 2×2 photonic switches is O(log(ϵ)/log(γ)), where γ=ρ²/(ρ²+4-4ρ). If one modifies the baseline architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2×2 photonic switches is reduced to O(log[log(ϵ)/log(γ)]). The required number of 2×2 photonic switches is essentially insensitive to the distribution of packet arrivals, but long delay lines are required for bursty traffic     

基于高性能运算PC集群综合优化技术研究

随着Pc集群技术在高性能运算地震资料处理领域的迅猛发展,如何提高PC集群的整体应用性能,成为业界普遍关注的技术难题。针对应用软件的具体需求,收集、整理集群节点的性能数据,定位影响作业运行效率的系统瓶颈,通过参数优化、硬件升级、系统定制和脚本开发等技术手段,全方位实现地震资料处理系统的最优化运行,从而达到提升PC集群系统整体性能的目的,同时也为高性能运算Pc集群的性能优化提供了可参考和借鉴的解决方案。     

A VLSI model for residue number system architectures

Combining the Residue Number System as a computational tool and VLSI as a fabrication medium promises to provide modular and cost efficient implementation of many digital signal processing algorithms. In this paper, a memory model has been developed. It is a low level model, which is used to derive relationships between the size of each modulus (in the chosen number system), and both chip area and time required for implementing the corresponding look-up tables. The memory model allows the selection of the most efficient layout for memories which do not have power of two dimensions. A set of multi-look-up table modules has been proposed as building block units for implementing digital signal processing algorithms. A procedure has been developed to optimize the area and time of those modules.     

A review:Photonics devices,architectures,and algorithms for optical neural computing

The explosive growth of data and information has motivated various emerging non-von Neumann computational approaches in the More-than-Moore era.Photonics neuromorphic computing has attracted lots of attention due to the fascinating advantages such as high speed,wide bandwidth,and massive parallelism.Here,we offer a review on the optical neural computing in our research groups at the device and system levels.The photonics neuron and photonics synapse plasticity are presented.In addition,we introduce several optical neural computing architectures and algorithms including photonic spiking neural network,photonic convolutional neural network,photonic matrix computation,photonic reservoir computing,and photonic reinforcement learning.Finally,we summarize the major challenges faced by photonic neuromorphic computing,and propose promising solutions and perspectives.     

路由器体系结构及其演变趋势

路 由器在ＩＰ网上处于至关重要的位置。随着网络带宽的迅速增加，用户对服务质量要求的提高，路由器技术也面临着新的变革。从路由器及发展趋势看，路由技术的发展已经与交换技术、宽带技术有机地结合在一起。路由器通常把数据包从一个数据链路中继到另一数据链路。路由调度是保证实时性业务服务质量和提高网络资源利用率的关键。为了中转数据包，路由器具有两个基本功能：路径判断和交换。随着互联网的飞速发展和宽带技术的不断出现，对路由器的性能提出的要求越来越高。 路由器的结构类型 从体系结构看，路由器经历了从单处理器到并行处…     

全IP UMTS的系统结构

UMTS（通用移动通信系统）有两个版本：R99和R00。R99版本或多或少是从2G系统结构逻辑演化而来；而R00则是完全的革新版，提出了许多新概念，具有许多新特征。在3GPP的UMTS标准制定过程中，出现了两种对3G标准的未来演进有重要影响的趋势。一种倾向于全IP的UMTS网络结构，这就是R00版本的基础。R00全IP的UMTS用分组交换替换了在R99版中仍使用的电路交换传输技术，并且在UMTS核心网上提供了对多媒体的支持。另一种趋势是朝向开放业务结构（OSA）的演进。它迫使网络运营商提供开放的标准接口，以便第三方业务供应商接入到他们…