Simulation study on a new dual-material nanowire MOS surrounding-gate transistor

In this paper, a novel field effect nanowire MOS transistor taking advantage of both dual-material gate and surrounding gate is proposed and performance characteristics are demonstrated numerically in detail. Surrounding-gate transistor is known to be used to enhance the electrostatic control of the channel, and dual-material-gate structure is extended from split-gate field effect transistor to obtain larger current and better short-channel performance. Three dimensional device simulations with Sentaurus Device are performed on this dual-material surrounding-gate transistor. Higher driving current, high ION/IOFF ratio and suppressed short-channel effects are obtained with this novel device structure.     

Fabrication and characterization of directly-assembled ZnO nanowire field effect transistors with polymer gate dielectrics

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.     

High-performance polycrystalline silicon thin-film transistors with oxide-nitride-oxide gate dielectric and multiple nanowire channels

This work presents a method to enhance the performance of polycrystalline silicon thin film transistors (poly-Si TFTs) by using an oxide-nitride-oxide (ONO) gate dielectric and the multiple nanowire channels structure. Experimental results indicate that the performance of the device was enhanced by using the ONO multilayer, because the ONO gate dielectric constant is increased compared to the conventional oxide gate dielectric. Additionally, the TFTs with a ten nanowire channel structure (NW-TFTs) have superior electrical characteristics compared to other TFTs. This is because a structure with more corners and a shorter radius has better gate control due to the corner effect.     

Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN (phi_TiN) slightly decreases with increasing nitrogen (N₂) gas flow ratio, R_N=N₂/(Ar+N₂) in the sputtering, from 17% to 100%. The experimental threshold voltage (V_th) dependence on the R_N shows that the more R_N offers the lower V_th for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different R_N showed that the more amount of nitrogen is introduced into the TiN films with increasing R_N, which suggests that the lowering of phi _TiN with increasing R_N should be related to the increase in nitrogen concentration in the TiN film. The desirable V_th shift from -0.22 to 0.22 V was experimentally confirmed by fabricating n⁺ poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TiN gate FinFET fabrication     

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-channel effects due to the coexistence of longer channel regions. There can be some design margin in the channel thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device width and SOI thickness. To determine the appropriate SOI thickness of FinFET, alternating current (AC) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay, as the drive current also increases and compensates for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current or thicker SOI are more favorable for the fixed S/D doping condition.     

The impact of structural parameters on the electrical characteristics of silicon nano wire transistor based on non equilibrium Green's function

In this paper we have used a fully ballistic quantum mechanical transport approach to analyse electrical characteristics of rectangular silicon nanowire field effect transistor in 7 nm gate length. We have investigated the impact of structural parameters of Gate all around Silicon nano wire transistor (GAA-SNWT) on its electrical characteristics in subthreshold regime. In particular we have shown the effect of increasing the Source/Drain and channel length (L(S), L(D) and L(Ch)) on short channel effects as well as change in body thickness and independent back gate voltage. We also investigate the effect of increasing the gate underlap on the electrical characteristics and on the switching speed of device. We show that if the Lun is increased the gate capacitance and DIBL will reduce while the I(ON)/I(OFF) ratio is increased.     

Impact of line width roughness on the matching performances of next-generation devices

It is now widely accepted that line width roughness (LWR) reduces transistor performances and is a critical factor, along side gate leakage and short-channel effects, for device scaling at the 45 nm technology node and beyond. As new process modules and device architecture options are emerging, we report on a methodology that has been developed to study the impact of line width and LWR uncertainties at the device level. By investigating the matching performances of both planar CMOS and FinFETs, we evaluate the sensitivity to roughness of important electrical parameters like the off-current or the threshold voltage.     

Realizing lateral wrap-gated nanowire FETs: controlling gate length with chemistry rather than lithography

An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling but has only been realized for vertically oriented nanowire transistors. We report a method for producing laterally oriented wrap-gated nanowire field-effect transistors that provides exquisite control over the gate length via a single wet etch step, eliminating the need for additional lithography beyond that required to define the source/drain contacts and gate lead. It allows the contacts and nanowire segments extending beyond the wrap-gate to be controlled independently by biasing the doped substrate, significantly improving the subthreshold electrical characteristics. Our devices provide stronger, more symmetric gating of the nanowire, operate at temperatures between 300 and 4 K, and offer new opportunities in applications ranging from studies of one-dimensional quantum transport through to chemical and biological sensing.     

Four-Terminal FinFETs Fabricated Using an Etch-Back Gate Separation

A novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigates. This process enabled co-fabrication of three-terminal (3T) and four-terminal (4T) FinFETs on a same chip. The fabricated 3T-FinFET shows excellent sub-threshold characteristics and drain induced barrier lowering (DIBL) value whereas the 4T-FinFET provides efficient V_th controllability. The effective V_th controllability with keeping a small sub-threshold slope has been confirmed in the synchronized double gate (DD) operation mode     

Cryogenic operation of FinFETs aiming at analog applications

FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold voltage, subthreshold slope and carrier mobility will be studied. Also some important figures of merit for analog circuit operation as for readout electronics, such as transconductance, output conductance and intrinsic voltage gain will be covered. It is demonstrated that the threshold voltage of undoped narrow FinFETs is less temperature-dependent than for a planar single-gate device with similar doping concentration. The temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L = 90 nm FinFET is degraded by 2 dB when the temperature reduces from 300 K to 100 K.     

A unified drain current model for nanoscale double-gate and surrounding-gate MOSFETs incorporating velocity saturation

A unified drain current model for undoped or lightly doped symmetric double-gate and surrounding-gate MOSFETs incorporating velocity saturation effect is proposed in this paper. The unified charge-based core model for undoped or lightly doped double-gate and surrounding-gate MOSFETs is presented first based on the previously published separate models. Caughey-Thomas engineering mobility model with its exponent factor n = 2 is then integrated self-consistently into the unified drain current model development of the two device structures. Extensive two dimensional and three dimensional device simulations are performed to validate the proposed model. Good agreements of the output and transfer characteristics between the unified model and the numerical simulations are obtained for both the double-gate and surrounding-gate MOSFETs. Symmetry property of the proposed unified current model is obtained with the exponent factor n = 2 in Cauhey-Thomas Model.     

Single-electron transistors based on gate-induced Si island for single-electron logic application

The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induced tunnel junctions, and controls the phase of the Coulomb oscillation. The capacitance between the sidewall gate and the Si island extracted from the Coulomb oscillation phase shift of the SETs with sidewall depletion gates on a silicon-on-insulator nanowire was independent of the Si island size, which is consistent with the device structure. The Coulomb oscillation phase shift of the fabricated SETs has the potential for a complementary operation. As a possible application to single-electron logic, the complementary single-electron inverter and binary decision diagram operation on the basis of the Coulomb oscillation phase shift and the tunable tunnel junctions were demonstrated.     

Electrical characteristic analysis using low-frequency noise in low-temperature polysilicon thin film transistors

This study carried out an electrical characteristic analysis using low-frequency noise (LFN) in top gate p-type low-temperature polysilicon thin film transistors (LTPS TFTs) with different active layer thicknesses between 40 nm and 80 nm. The transfer characteristic curves show that the 40-nm device has better electrical characteristics compared with the 80-nm device. The carrier number fluctuation, with and without correlated mobility fluctuation model in both devices, has modeled well the measured noise. On the other hand, the trap density and coulomb scattering in the 40-nm device are smaller compared with the 80-nm device. To confirm the effectiveness of the LFN noise analysis, the trap densities at a grain boundary are extracted using in both devices the similar methods of Proano et al. and Levinson et al. That is, coulomb scattering, caused by the trapped charges at or near the interface, has a greater effect on the device with inferior electrical properties. Based on the LFN and the quantitative analysis of the trap density at a grain boundary, the interface traps between the active layer and the gate insulator can explain the devices' electrical degradation.     

Extremely scaled 3-dimensional multiple-gate technologies for terabit era

In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time.     

High resolution scanning gate microscopy measurements on InAs/GaSb nanowire Esaki diode devices

Gated transport measurements are the backbone of electrical characterization of nanoscale electronic devices. Scanning gate microscopy （SGM） is one such gating technique that adds crucial spatial information, accessing the localized properties of semiconductor devices. Nanowires represent a central device concept due to the potential to combine very different materials. However, SGM on semiconductor nanowires has been limited to a resolution in the 50-100 nm range. Here, we present a study by SGM of newly developed III-V semiconductor nanowire InAs/GaSb heterojunction Esaki tunnel diode devices under ultra-high vacuum. Sub-5 nm resolution is demonstrated at room temperature via use of quartz resonator atomic force microscopy sensors, with the capability to resolve InAs nanowire facets, the InAs/GaSb tunnel diode transition and nanoscale defects on the device. We demonstrate that such measurements can rapidly give important insight into the device properties via use of a simplified physical model, without the requirement for extensive calculation of the electrostatics of the system. Interestingly, by precise spatial correlation of the device electrical transport properties and surface structure we show the position and existence of a very abrupt （〈10 nm） electrical transition across the InAs/GaSb junction despite the change in material composition occurring only over 30-50 nm. The direct and simultaneous link between nanostructure composition and electrical properties helps set important limits for the precision in structural control needed to achieve desired device performance.     

Electrical characterization of composition modulated In(1-x)Sb(x) nanowire field effect transistors by scanning gate microscopy

In this work high quality crystalline In(1_x)Sb(x) nanowires (NWs) are synthesized via a template-based electrochemistry method. Energy dispersive spectroscopy studies show that composition modulated In(1-x)Sb(x) (x approximately 0.5 or 0.7) nanowires can be attained by selectively controlling the deposition potential during growth. Single In(1-x)Sb(x) nanowire field effect transistors (NW-FETs) are fabricated to study the electrical properties of as-grown NWs. Using scanning gate microscopy (SGM) as a local gate the I(ds)-V(ds) characteristics of the fabricated devices are modulated as a function of the applied gate voltage. Electrical transport measurements show n-type semiconducting behavior for the In0.5Sb0.5 NW-FET, while a p-type behavior is observed for the In0.3Sb0.7 NW-FET device. The ability to grow composition modulated In(1-x)Sb(x) NWs can provide new opportunities for utilizing InSb NWs as building blocks for low-power and high speed nanoscale electronics.     

ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al(2)O(3) gate oxides

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al(2)O(3) tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8?V was observed in its drain current versus gate voltage (I(DS)-V(GS)) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper.     

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.     

Measuring the capacitance of individual semiconductor nanowires for carrier mobility assessment

Capacitance-voltage characteristics of individual germanium nanowire field effect transistors were directly measured and used to assess carrier mobility in nanowires for the first time, thereby removing uncertainties in calculated mobility due to device geometries, surface and interface states, and gate dielectric constants and thicknesses. Direct experimental evidence showed that surround-gated nanowire transistors exhibit higher capacitance and better electrostatic gate control than top-gated devices, and are the most promising structure for future high performance nanoelectronics.     

Electrical actuation and readout in a nanoelectromechanical resonator based on a laterally suspended zinc oxide nanowire

In this paper, we present experimental results describing enhanced readout of the vibratory response of a doubly clamped zinc oxide (ZnO) nanowire employing a purely electrical actuation and detection scheme. The measured response suggests that the piezoelectric and semiconducting properties of ZnO effectively enhance the motional current for electromechanical transduction. For a doubly clamped ZnO nanowire resonator with radius ~10 nm and length ~1.91 μm, a resonant frequency around 21.4 MHz is observed with a quality factor (Q) of ~358 in vacuum. A comparison with the Q obtained in air (~242) shows that these nano-scale devices may be operated in fluid as viscous damping is less significant at these length scales. Additionally, the suspended nanowire bridges show field effect transistor (FET) characteristics when the underlying silicon substrate is used as a gate electrode or using a lithographically patterned in-plane gate electrode. Moreover, the Young's modulus of ZnO nanowires is extracted from a static bending test performed on a nanowire cantilever using an AFM and the value is compared to that obtained from resonant frequency measurements of electrically addressed clamped–clamped beam nanowire resonators.