Subthreshold behavior of thin-film LPCVD PolySilicon MOSFET's

A physical model that characterizes the subthreshold drain current (gate-voltage swing) and the threshold voltage of thin-film LPCVD polysilicon MOSFET's is developed and supported experimentally. The model describes the influence of the grain boundaries and of the charge coupling between the front and back gates on the subthreshold behavior. Main predictions are that the gate-voltage swing depends strongly on grain-boundary properties but weakly on the charge-coupling effects, that the threshold voltage depends strongly on grain-boundary properties and charge-coupling effects, and that the charge-coupling effects diminish as the grain-boundary trap density, the thickness of the film, or the doping density in the film increases. Comparisons of model predictions and measured data for passivated (hydrogenated) and unpassivated devices indicate quantitatively how hydrogenation reduces the trap density and increases the carrier mobility in the channel.     

高温CMOS数字集成电路直流传输特性的分析

分析了高温CMOS倒相器和门电路的直流传输特性,建立了相应的解析模型。根据分析,高温MOSFET阈值电压和载流子迁移率的降低,以及MOSFET漏端pn结泄漏电流的增加引起了CMOS倒相器和门电路直流传输特性劣化。在MOSFET漏端pn结泄漏电流的影响下,高温CMOS倒相器和门电路的输出高电平下降,低电平上升,导致了电路的功能失效。给出的理论模型和实验结果一致。     

Enhanced low-temperature corner current-carrying inherent toshallow trench isolation (STI)

The subthreshold hump in the current-voltage (I-V) characteristics caused by the current-carrying corner in shallow-trench-isolated (STI) n-channel MOSFET's is significantly enhanced at reduced temperatures. Numerical simulations show that the sensitivity of the corner channel's threshold voltage to temperature is smaller than that of the center channel's threshold voltage. This, together with the reduced subthreshold swing at low temperatures, contribute to an enhanced subthreshold hump, and is potentially important for emerging cryogenic applications     

Physical subthreshold MOSFET modeling applied to viable design ofdeep-submicrometer fully depleted SOI low-voltage CMOS technology

An insightful study of the subthreshold characteristics of deep-submicrometer fully depleted SOI MOSFET's, based on two-dimensional numerical (PISCES) device simulations, shows that the gate swing and off-state current are governed by gate bias-dependent source/drain charge sharing, which controls back-channel as well as front-channel conduction. The insight from this study guides the development of a physical, two-dimensional analytic model for the subthreshold current and charge, which is linked to our strong-inversion formalism in SOISPICE for circuit simulation. The model is verified by PISCES simulations of scaled devices. The utility of the model in SOISPICE is demonstrated by using it to define a viable design for deep-submicrometer fully depleted SOI CMOS technology based on simulated speed and static power in low-voltage digital circuits     

A subthreshold model of the narrow-gate effect in MOSFET's

The subthreshold softening characteristic of MOSFET's due to the narrow-gate effect has been investigated based on the two-dimensional (2-D) numerical solution of the Poisson equation and device physics. Numerical results taken on stepped-oxide MOSFET's with different gate widths show that a narrower gate width device tends to give higher cut-off voltage. Two parameters account for the softening of the subthreshold characteristics: the subthreshold slope of the drain conductance-gate voltage characteristic and the effective channel width. Both parameters can be extracted easily from the theoretical 2-D computed or experimental drain conductance-gate voltage characteristics. A two-parameter analytical approximation formula for narrow-gate MOSFETs operating in the subthreshold range is thus proposed and tested against exact 2-D numerical results, showing good accuracy. This model is the first one ever reported.     

Back-gate bias enhanced band-to-band tunneling leakage in scaledMOSFET's

The drain leakage current in MOSFET's in the present standard process is separated into three distinct components: the subthreshold conduction, the surface band-to-band tunneling (BTBT), and the bulk BTBT. Each of the three shows different dependencies on back-gate bias. As a result, the bulk BTBT, increasing exponentially with increasing the magnitude of back-gate reverse bias, promptly dominates the drain leakage. Additional experiment highlights the effect of the increased bulk dopant concentrations as in next-generation scaled MOSFET's on the bulk BTBT. This sets the bulk BTBT a significant constraint to the low-voltage, low-power, high-density CMOS integrated circuits employing the back-gate reverse bias. In this work, the measured drain leakage of interest is successfully reproduced by two-dimensional (2-D) device simulation     

Short channel characteristics of Si MOSFET with extremely shallowsource and drain regions formed by inversion layers

The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's are experimentally investigated. These extremely shallow junctions are realized in MOSFET's with a triple-gate structure. Two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source and drain. Significant improvement in threshold voltage roll-off and punchthrough characteristics are obtained in comparison with conventional MOSFET's whose junctions are formed by ion implantation: threshold voltage roll off is suppressed down to a physical gate length of 0.1 μm while punchthrough is suppressed down to 0.07 μm, the minimum pattern size delineated. It is also demonstrated experimentally that the carrier concentrations in the source and drain do not have any influence on the short channel effects     

Investigation of the Electrical and Thermal Performance of SOI MOSFETs with Modified Channel Engineering

In this paper, we present a novel type of channel doping engineering, using a graded doping distribution, that improves the electrical and thermal performance of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), according to simulations that we have performed. The results obtained include a reduction in the self-heating effect, a reduction in leakage currents due to the suppression of short-channel effects (SCEs), and a reduction in hot-carrier degradation. We term the proposed structure a modified-channel-doping SOI (MCD-SOI) MOSFET. The main reason for the reduction in the self-heating effect is the use of a lower doping density near the drain region in comparison with conventional SOI MOSFETs with a uniform doping distribution. The most significant reason for the leakage current reduction in the MCD-SOI structure is the high potential barrier near the source region in the weak inversion state. The SCE factors, including the drain-induced barrier lowering, subthreshold swing, and threshold voltage roll-off, are improved. A highly reliable structure is achieved owing to the lower doping density near the drain region, which reduces the peak electric field and the electron temperature.     

A new approach to analytically solving the two-dimensional Poisson's equation and its application in short-channel MOSFET modeling

An analytical solution for the potential distribution of the two-dimensional Poisson's equation with the Dirichlet boundary conditions has been obtained for the MOSFET device by using Green's function method and a new transformation technique, in which the effects of source and drain junction curvature and depth are properly considered. Based on the calculated potential distribution, the subthreshold current considering the drain-induced barrier lowering effects has been computed by a simple current equation that considers only the diffusion component with an effective length determined by the potential distribution at the SiO2-Si interface. From the calculated subthreshold current, the threshold voltage of the MOSFET's is determined. It has been verified that the dependences of the calculated threshold voltage and subthreshold current on device channel length, drain, and substrate biases are in good agreement with those computed by whole two-dimensional numerical analysis and experimental data.     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

WSi_2栅和Si栅CMOS／BESOI的高温特性分析

用厚膜ＢＥＳＯＩ（ＢｏｎｄｉｎｇａｎｄＥｔｃｈ－ｂａｃｋＳｉｌｉｃｏｎ－Ｏｎ－Ｉｎｓｕｌａｔｏｒ）制备了ＷＳｉ２栅和Ｓｉ栅４００７ＣＭＯＳ电路，在室温～２００℃的不同温度下测量了其Ｐ沟、Ｎ沟ＭＯＳＦＥＴ的亚阈特性曲线，分析了阈值电压和泄漏电流随温度的变化关系。     

Flicker noise in CMOS transistors from subthreshold to stronginversion at various temperatures

Flicker noise is the dominant noise source in silicon MOSFET's. Even though considerable amount of work has been done in investigating the noise mechanism, controversy still exists as to the noise origin. In this paper, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage changing from linear to saturation regions of operation. The measurement temperature was varied from room temperature down to 5 K. Experimental results consistently suggest that 1/f noise in n-channel devices is dominated by carrier-density fluctuation while in p-channel devices the noise is mainly due to mobility fluctuation     

An analytical threshold voltage and subthreshold current model forshort-channel MESFETs

Short-channel effects on the subthreshold behavior are modeled in self-aligned gate MESFETs with undoped substrates through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of the short-channel effects in MESFETs with doped and undoped substrates indicates that channel lengths will be limited to 0.15-0.2 μm by subthreshold conduction. Besides offering insight into the device physics of the short-channel effects in MESFETs, the model provides a useful basis for accurate analysis and simulation of small-geometry GaAs MESFET digital circuits     

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero VGin thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.     

Intrinsic MOSFET parameter fluctuations due to random dopantplacement

Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultrasmall-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte Carlo simulator. These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard and maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40 and 600 mV, 10 and 100%, 2 and 20 mV/dec, and 10 and 10⁸%, respectively, in the 0.07 μm, 0.9 V complementary metal-oxide-semiconductor (CMOS) technology generation with 1.3-64 billion transistors on a chip in 2010. While these deviations can be reduced to some degree by selecting optimal values of channel width, the associated penalties in dynamic and static power, and in packing density demand improved MOSFET structures aimed at minimizing parameter deviations     

Analytical modelling for the current-voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs

An analytical drain current model for undoped (or lightly-doped) symmetric double-gate (DG) MOSFETs is presented. This model is based on the subthreshold leakage current in weak inversion due to diffusion of carriers from source to drain and an analytical expression for the drain current in strong inversion of long-channel DG MOSFETs, both including the short-channel effects. In the saturation region, the series resistance, the channel length modulation, the surface-roughness scattering and the saturation velocity effects were also considered. The proposed model has been validated by comparing the transfer and output characteristics with simulation and experimental results.     

Electrical Characteristics of the HfAlON Gate Dielectric With Interfacial UV-Ozone Oxide

In this letter, the electrical properties of a HfAlON dielectric with UV-O₃ interfacial oxide were comprehensively studied and then compared with those of a HfAlON dielectric with interfacial chemical oxide. In the comparison of dielectric characteristics including leakage current density, transconductance, subthreshold swing, saturation drain current, effective electron mobility, and constant voltage stress reliabilities, the results clearly indicate that high-density interfacial UV-O₃ oxide is beneficial in reducing both bulk and interface traps as well as diminishing stress-induced trap generation, and possesses a high potential to be integrated with further high-kappa dielectric applications.     

A comprehensive study of hot carrier stress-induced drain leakagecurrent degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V_gs such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Å) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Å) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation