Memory effects of all‐solution‐processed oxide thin‐film transistors using ZnO nanoparticles

Abstract— Non‐volatile memory effects of an all‐solution‐processed oxide thin‐film transistor (TFT) with ZnO nanoparticles (NPs) as the charge‐trapping layer are reported. The device was fabricated by using a soluble MgInZnO active channel on a ZrHfO^x gate dielectric. ZnO NPs were used as the charge‐trapping site at the gate‐insulator—channel interface, and Al was used for source and drain electrodes. Transfer characteristics of the device showed a large clockwise hysteresis, which can be used to demonstrate its memory function due to electron trapping in the ZnO NP charge‐trapping layer. This memory effect has the potential to be utilized as a memory application on displays and disposable electronics.     

Impact of ZnO gate interfacial layer on piezoelectric response of AlGaN/GaN C-HEMT based ring gate capacitor

We report on a piezoelectric response investigation of AlGaN/GaN circular high electron mobility transistor (C-HEMT) based ring gate capacitor as a new stress sensor device to be potentially applied for dynamic high-pressure sensing. A ring gate capacitor of C-HEMT with an additional ZnO gate interfacial layer was used to measure the changes in the piezoelectric charge induced directly by the variation of piezoelectric polarization of both gate piezoelectric layers (AlGaN, ZnO) for harmonic loading at different excitation frequences. Our experimental results show that about 10 nm thick piezoelectric ZnO layer grown on ring gate/AlGaN interface of C-HEMT can yield almost a 60% increase in the piezoelectric detection sensitivity of the device due to its higher piezoelectric coefficient. A three-dimensional CoventorWare simulation is carried out to confirm the increase in the measured piezoelectric response of ZnO based ring gate capacitor of C-HEMT.     

Fabrication of poly‐Si complementary metal oxide semiconductor inverter by all sputtering deposition process

Direct current sputtering was used for deposition of Si film for precursor film of excimer laser annealing, n⁺‐Si/p⁺‐Si film for source/drain contact, and SiO₂ film for gate insulator of polycrystalline silicon thin‐film transistor. Using these methods, poly‐Si thin‐film complementary metal oxide semiconductor inverter was fabricated by all sputtering process for the first time. The field‐effect mobility was, respectively, 6.5 and 12.5 cm²/Vs for n‐TFTs and p‐TFTs. This inverter exhibits a full rail‐to‐rail swing and abrupt voltage transfer characteristics over the entire voltage range, and the output voltage gain was ~117 at V_dd = 20 V.     

Comparative study of source–drain contact metals for amorphous InGaZnO thin‐film transistors

In this work, we compared the thin‐film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom‐gate bottom‐contact (BGBC) and bottom‐gate top‐contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a‐IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal‐containing deposits in the channel and the contact oxidation during a‐IGZO layer sputtering in the presence of S/D metal. In bias‐stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal‐containing deposits at the backchannel during the final the SiO₂ passivation.     

Fabrication of 5.8‐in. OTFT‐driven flexible color AMOLED display using dual protection scheme for organic semiconductor patterning

Abstract— A 5.8‐in. wide‐QQVGA flexible color active‐matrix organic light‐emitting‐diode (AMOLED) display consisting of organic thin‐film transistors (OTFTs) and phosphorescent OLEDs was fabricated on a plastic film. To reduce the operating voltage of the OTFTs, Ta₂O₅ with a high dielectric constant was employed as a gate insulator. Pentacene was used for the semiconductor layer of the OTFTs. This layer was patterned by photolithography and dry‐etched using a dual protection layer of poly p‐xylylene and SiO₂ film. Uniform transistor performance was achieved in the OTFT backplane with QQVGA pixels. The RGB emission layers of the pixels were formed by vacuum deposition of phosphorescent small molecules. The resulting display could clearly show color moving images even when it was bent and operated at a low driving voltage (below 15 V).     

Power saving through state retention in IGZO‐TFT AMOLED displays for wearable applications

We present a qHD (960 × 540 with three sub‐pixels) top‐emitting active‐matrix organic light‐emitting diode display with a 340‐ppi resolution using a self‐aligned IGZO thin‐film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven‐layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low‐temperature polycrystalline silicon. By using an IGZO thin‐film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low‐refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

Oxide engineering of ZnO thin‐film transistors for flexible electronics

Abstract— In this paper, we show that ZnO thin‐film transistors (TFTs) are potentially a higher performance alternative to organic and amorphous‐Si TFTs for macroelectronics on plastic substrates. Specifically, we fabricated nanocrystalline ZnO thin‐film transistors using low‐temperature processing, compatible with flexible electronics on plastic substrates. The ZnO semiconductor was rf magnetron sputtered, and the Al₂O₃ gate dielectric was deposited either by electron‐beam evaporation or atomic layer deposition. By controlling the partial pressure of oxygen pO₂) during ZnO sputtering, we could engineer the field‐effect mobility of ZnO transistors to be between 2 and 42 cm²/V‐sec, attractive for high‐performance electronic applications. We contend that pO₂ controls the oxygen‐vacancy content or stoichiometry of ZnO, and that allows control of transistor field‐effect mobility. Although most of the devices described here were fabricated on Si substrates, devices we made on a thin (50 μm thick) polyimide substrate had about equivalent performance, affirming the compatibility of our processes with plastic substrates. Finally, we show that properties of our nanocrystalline ZnO transistors can be explained by transport models that account for grain‐boundary trapping of mobile carriers.     

Fabrication of ultraviolet photoconductive sensor using a novel aluminium-doped zinc oxide nanorod-nanoflake network thin film prepared via ultrasonic-assisted sol-gel and immersion methods

Unique and novel thin films with aluminium (Al)-doped zinc oxide (ZnO) nanostructures consisting of nanorod-nanoflake networks were prepared for metal-semiconductor-metal (MSM)-type ultraviolet (UV) photoconductive sensor applications. These nanostructures were grown on a glass substrate coated with a seed layer using a combination of ultrasonic-assisted sol-gel and immersion methods. The synthesised ZnO nanorods had diameters varying from 10 to 40 nm. Very thin nanoflake structures were grown vertically and horizontally on top of the nanorod array. The thin film had good ZnO crystallinity with a root mean square roughness of approximately 13.59 nm. The photocurrent properties for the Al-doped ZnO nanorod-nanoflake thin films were more than 1.5 times greater than those of the seed layer when the sensor was illuminated with 365 nm UV light at a density of 5 mA/cm². The responsivity of the device was found to be dependent on the bias voltage. We found that similar photocurrent curves were produced over eight cycles, which indicated that the UV sensing capability of the fabricated sensor was highly reproducible. Our results provide a new approach for utilising the novel structure of Al-doped ZnO thin films with a nanorod-nanoflake network for UV sensor applications. To the best of our knowledge, UV photoconductive sensors using Al-doped ZnO thin films with a nanorod-nanoflake network have not yet been reported.     

Vertically integrated,double stack oxide TFT layers for high‐resolution AMOLED backplane

We developed a novel vertically integrated, double stack oxide thin‐film transistor (TFT) backplane for high‐resolution organic light‐emitting diode (OLED) displays. The first TFT layer is bulk‐accumulation mode, and the second TFT layer is a single gate with back‐channel etched structure. The extracted mobilities and threshold voltages are higher than 10 cm²/Vs and 0 ~ 1 V, respectively. Both TFTs are found to be extremely stable under the bias and temperature stress. The gate driver with width of 530 μm and a pitch of 18.6 μm was developed, exhibiting well shifted signal up to the last stage of 900 stages without output degradation, which could be used for 1360 ppi TFT backplane.     

Single-layer thin-film transistor analysis and design

A set of direct current (DC) analytical equations is formulated for the analysis and design of a single-layer thin-film transistor (TFT). For a specified TFT structure, drain current is calculated as a function of drain and gate voltage (taking the source as ground) according to the Enz, Krummenacher, Vittoz (EKV) compact model. One model parameter function is required to implement this EKV-based equation, that is, drift mobility as a function of gate voltage. Drift mobility is evaluated as a consequence of accumulation layer electrostatics assessment of the TFT structure specified. In order to implement the model, three semiconductor properties (low-frequency (static) relative dielectric constant, free electron concentration, and maximum (no trapping) mobility), two structure properties (insulator capacitance density and TFT width-to-length ratio), and one physical operating parameter (temperature) must be specified. Optimal TFT mobility performance is achieved when the thickness of the semiconductor channel layer is constrained to be less than 2.22 times the channel layer Debye length such that “short-base” TFT operation obtains. Additionally, higher mobility TFT performance is obtained by selecting a channel layer with a small electron effective mass, reducing channel layer trap density, reducing channel layer thickness, reducing the free electron concentration, and/or increasing gate capacitance density.     

基于BOE硅腐蚀现象的硅纳米线制作

介绍一种硅纳米线制作方法.在SOI顶层硅上制作硅纳米梁,通过离子注入形成pnp结构,利用新发现的没有特殊光照时BOE溶液腐蚀pn结n型区域现象,结合BOE溶液氧化硅腐蚀,实现硅纳米线制作.制作完全采用传统MEMS工艺,具有工艺简单,成本低,可控,可靠性好,可批量制作等优点.利用该方法制作出了厚50 nm,宽100 nm的单晶硅纳米线,制作的纳米线可用于一维纳米结构电学性能研究、谐振器研究等.     

The new route for realization of 1‐μm‐pixel‐pitch high‐resolution displays

A new pixel structure for the realization of a 1‐μm‐pixel‐pitch display was developed. This structure, named vertically stacked thin‐film transistor (VST), was based on the conventional back‐channel etched thin‐film transistor (TFT), but all the layers except the horizontal gate line were vertically stacked on the embedded data line, enabling the implementation of high‐resolution display panels. The VST device with a channel length of 1 μm showed a high field effect mobility of more than 50 cm²/Vs and low subthreshold slope of 78 mV per decade. It also shows a high uniform electrical characteristic over the entire 6‐in. wafer. The development of a new pixel architecture is expected to enable the implementation of 1‐μm‐pixel‐pitch high‐resolution displays such as spatial light modulators for digital holograms.     

A Laterally Movable Gate Field Effect Transistor

A laterally movable gate field effect transistor (LMGFET) device that directly couples lateral mechanical gate motion to drain current of a FET is presented in this paper. Lateral motion of the FET gate results in a change in channel width, keeping the channel length and the gap between the gate and the oxide layer constant. This results in a change in channel current that, in principle, is linearly proportional to mechanical motion. The operating principle of an LMGFET, along with details of the fabrication process for a depletion-type LMGFET device, is described. Fabricated LMGFET shows an average drain current sensitivity to gate motion of $-5.8 muhbox{A}/muhbox{m}$ at $V_{rm DS} = 20 hbox{V}$ and $V_{rm GS} = 0 hbox{V}$ for 60-$muhbox{m}$ gate motion. A model for the fabricated LMGFET is developed based on electrical measurements. The device shows promise both as a sensor and as an actuator in MEMS and other related applications.$hfill$ [2008-0147]      

Current and future technology of low‐temperature poly‐Si TFT‐LCDs

Abstract— The state of the art of large‐area low‐temperature TFT‐LCDs will be reported in this paper. High‐performance poly‐Si TFTs are expected to realize various applications such as system display where various signal‐processing functions are added to the display. In the past few years, low‐temperature poly‐Si thin‐film‐transistor (LTPS TFT) technology has made great progress, especially in the areas of excimer laser annealing (ELA) of high‐quality poly‐Si film, ion doping for large‐area doping, and high‐quality gate SiO₂ film formation by using the low‐temperature PE‐CVD method. Also, technology trends and possible applications, such as a system displays, will be discussed.     

Development of 8‐in. oxide‐TFT‐driven flexible AMOLED display using high‐performance red phosphorescent OLED

An 8‐in. flexible active‐matrix organic light‐emitting diode (AMOLED) display driven by oxide thin‐film transistors (TFTs) has been developed. In‐Ga‐Zn‐O (IGZO)‐TFTs used as driving devices were fabricated directly on a plastic film at a low temperature below 200 °C. To form a SiO_x layer for use as the gate insulator of the TFTs, direct current pulse sputtering was used for the deposition at a low temperature. The fabricated TFT shows a good transfer characteristic and enough carrier mobility to drive OLED displays with Video Graphic Array pixels. A solution‐processable photo‐sensitive polymer was also used as a passivation layer of the TFTs. Furthermore, a high‐performance phosphorescent OLED was developed as a red‐light‐emitting device. Both lower power consumption and longer lifetime were achieved in the OLED, which used an efficient energy transfer from the host material to the guest material in the emission layer. By assembling these technologies, a flexible AMOLED display was fabricated on the plastic film. We obtained a clear and uniform moving color image on the display.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

Influence of channel‐deposition conditions and gate insulators on performance and stability of top‐gate IGZO transparent thin‐film transistors

Abstract— Amorphous‐oxide‐semiconductor thin‐film transistors (TFTs) have gained wide attention in recent years due to their many merits. In this paper, a series of top‐gate transparent thin‐film transistors (TFTs) based on amorphous‐indium—gallium—zinc—oxide (a‐IGZO) semiconductors have been fabricated and investigated. Specifically, low‐temperature SiNx and SiOx were used as the gate insulator and different Ar/O² gas‐flow ratios were used for a‐IGZO channel deposition to study the influences of gate insulators and channel‐deposition conditions. In addition to the investigation of device performance, the stability of these TFTs was also examined by applying constant‐current stressing. It was found that a high mobility of 30‐45 cm²/V‐sec and small threshold‐voltage shift in constant‐current stressing can be achieved using SiNx with suitable hydrogen‐content stoichiometry as the gate insulator and the carefully adjusted Ar/O² flow ratio for channel deposition. These results may be associated with hydrogen incorporation into the channel, the lower defect trap density, and the better water/oxygen barrier properties (impermeability) of the low‐temperature SiNx.     

A vertical structure photodetector based on all‐inorganic perovskite quantum dots

In this work, the vertical structure photodetector based on CsPbBr₃ quantum dots (QDs) with a structure of indium tin oxide (ITO)/zinc oxide (ZnO)/CsPbBr₃ QDs/Au is reported. In this device, CsPbBr₃ QDs film works as the light‐harvesting layer, and ZnO QDs film acts as the electron transport channel, which can extract the electron efficiently and improve the quality of CsPbBr₃ QDs film. As a result, the on/off ratio, detectivity and rise time (decay time) of CsPbBr₃/ZnO hybrid photodetector are measured to be 2.4 × 10⁶, 2.25 × 10¹¹, and 62 milliseconds (82 ms) under 0‐V bias. This work inspires the development of vertical structure photodetectors based on the all‐inorganic perovskite QDs.     

Spice model for detection of dynamic threshold voltage shift during failure analysis of oxide TFT‐based AMD gate drivers

We present an accelerated SmartSpice model that can detect dynamic threshold voltage shift (ΔV_th)‐related failure of an oxide thin‐film transistor (TFT)‐based gate driver. During gate driver operation, the alternating HIGH and LOW input signals repeatedly stress and relax the TFT components of the gate driver. Because oxide TFTs do not recover completely during the LOW input level, ΔV_th cumulated during the HIGH input levels may result in failure of gate drivers. For correct failure analysis, a TFT model that can detect dynamic ΔV_th is, therefore, needed to replace current TFT models, as they cannot account for dynamic ΔV_th. The model presented herein works correctly with varying temperature and input signals of any shape.