基于分段线性函数的功放模型及数字预失真应用

为了克服通信系统中功率放大器的非线性和记忆效应,数字预失真技术成为研究的热点。提出一种基于分段线性函数的多项式模型,与广义记忆多项式模型相比,我们把多项式中的高阶项转换为分段求和项,消除了高阶相乘带来的不稳定性,同时由于分段阈值的存在,该模型的适用性和稳定性均有所提高。把功放模型应用于数字预失真结构中的实验结果表明:与广义记忆多项式模型相比,分段线性函数模型所需系数要少40%,邻信道功率比提高约1dB,归一化均方误差提高约8dB,因此该模型在数字预失真方面具有较好的效果。     

一种具有普适性的功放线性化预失真方案

为解决功率放大器的非线性问题,提高功放效率,提出了一种能够应用于多种类型功放的间接结构多项式数字基带预失真方案。采取间接预失真结构规避了功放的辨识过程,选择记忆多项式模型作为预失真器能够线性化多种类型的功放,同时采用改进的抑制牛顿算法减少了参数的迭代次数和运算量。以64QAM信号作为输入,对几种典型的功放模型进行数字预失真处理,通过MATLAB仿真分析预失真前后信号的功率谱变化以及ACPR值的改变,表明该方案能够取得比较理想的预失真效果,同时证明了此预失真方案具有一定的普适性。     

Volterra series‐based model for concurrent dual‐band power amplifier using dynamic memory depth

In this article, a dynamic dual‐band baseband equivalent Volterra (DDBE) model is proposed to compensate the nonlinear distortions of the concurrent dual‐band power amplifier (PA). The DDBE model is obtained by improving the discretized dual‐band baseband equivalent Volterra model which can describe the output characteristics of concurrent dual‐band PA completely in theory but is lack of practicability. Three simplification rules are proposed in the article, and the relevance between in‐band intermodulation and in‐band cross modulation is employed to simplify the establishment complexity of the model. Then the dynamic kernels are categorized into three groups, and based on this, DDBE models with different level dynamical kernels are derived. In addition, draw on the experience of single‐band PA behavioral model, even‐order kernels are introduced into DDBE models. Digital predistortion performances of a wideband PA, which works in concurrent dual‐band mode, are evaluated to verify the feasibility and advantages of the proposed model.     

一种新型射频功放建模结构LMEC研究及预失真应用

针对现代无线通信系统中射频功率放大器的强非线性特征, 提出了一种高精度、低复杂度的LMEC（LUT-MP-EMP-CIMT）模型。该模型由查找表（LUT）、记忆多项式（MP）、包络记忆多项式（EMP）及记忆交叉项（CIMT）并联构成。与并联双非线性两箱模型（PTNTB）相比, LMEC模型增加了EMP子模型和CIMT子模型。实验结果表明, LMEC模型能带来更好的建模精度和线性化效果, 较MP模型的建模精度提升了2. 9 dB, 邻信道功率比（ACPR）值降低约5 dB; 较PTNTB模型精度提升了1. 1 dB, ACPR值降低约3 dB; 与通用记忆多项式模型（GMP）相比性能相近, 但减少了50%的系数。     

宽带RF功率放大器的预失真线性化技术综述

随着无线需求和无线业务的不断增加,传输信号必将不断向高速率宽带宽发展。在宽带应用中,由于传输信号带宽增加,RF功率放大器不同于窄带输入下的无记忆特性,将表现出与频率有关的记忆非线性特性。针对宽带功率放大器线性化的记忆预失真技术成为当前研究的一个热点,综述了宽带RF功率放大器的预失真线性化技术的研究进展,详细介绍和分析了目前最主要的几种记忆预失真器的模型和对应的自适应预失真方案,最后给出了今后的研究方向。     

Frequency domain data based model extraction for band‐limited digital predistortion of wideband RF power amplifiers

Bandwidth constraints pose significant challenges to linearization of wideband RF power amplifiers (PAs) with digital predistortion (DPD). A recently proposed band‐limited DPD scheme uses a band‐limited modeling technique to eliminate the bandwidth constraints and reduce DPD implementation cost. However, time consuming convolution operations are involved for model extraction in this time domain data based band‐limited modeling method. In this article, band‐limited model extraction is formulated as a generalized least squares problem and investigated from a frequency domain perspective. A frequency domain data based model extraction method is proposed, which greatly reduces the computational complexity for extracting band‐limited DPD model parameters. A 10 W GaN HEMT inverse class‐F PA excited by a 20 MHz four‐carrier WCDMA signal and a 40 MHz two‐carrier LTE signal is tested to validate the method. Experimental results show that the computationally efficient frequency domain data based model extraction method for band‐limited DPD provides as good linearization performance as the time domain data based method. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:412–420, 2014.     

基于并行演化计算的记忆非线性功率放大器数字预失真研究

自适应数字预失真是克服高功率放大器非线性失真最有前途的一项技术。为提高预失真的效率和效果,引入并行计算平台下的演化计算技术,提出了基于PSO算法预训练神经网络的方法,给出了算法软件实现的基本流程。在所述基础上,采用带抽头延时的双入双出三层前向神经网络结构,根据非直接学习结构和反向传播算法实现自适应,可同时补偿放大器的记忆失真和非线性失真的预失真技术。仿真实验表明,通过与无PSO预训练算法的相比,基于PSO预训练的神经网络训练算法有更好的性能。     

Low complexity output generalized memory polynomial model for digital predistortion of RF power amplifiers

A novel output generalized memory polynomial (OGMP) behavioral model was proposed in this article, which is based on the previous output signal for digital predistortion (DPD) of power amplifiers (PA). Traditional MP or GMP model use polynomials of the previous input signal to characterize memory effect. Although the OGMP model use polynomials of the previous output signal to characterize memory effect. Using the previous output signal to characterize polynomials of the previous input signal, the number of coefficients will decrease. Measurement results show that the proposed OGMP model can achieve the similar effect with less coefficients. In detail, the complexity of OGMP model reduced by about 50% comparing with MP model. Compared with GMP model, the complexity of OGMP model reduced by about 60% with the similar effect.     

An accurate physical knowledge‐based model for behavioral modeling and digital predistortion of power amplifiers

The objective of this article is to present an accurate model for behavioral modeling and digital predistortion of power amplifiers (PAs) using physical knowledge. Starting with the physically meaningful block model, we present a novel approach to simplify the block model and propose a simplified physical knowledge‐based (SPK) model. The SPK model's performance was experimentally assessed by two types of PAs (a LDMOS Doherty PA and a GaN Doherty PA) and two signals (a single carrier 16QAM signal and a 2‐carrier WCDMA signal). All experimental results prove the superiority of the SPK model. Compared with the 1st‐dynamic deviation reduction (DDR) approach and the 2nd‐simplified DDR approach, the SPK approach achieves average ACPR improvements of 4.4 dB and 2.5 dB, respectively. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE 23: 682–689, 2013.     

一种适用于射频数字功放的量化策略

为了提升射频数字功放整体效率,需要降低前端△∑调制器(DSM)输出的平均切换频率,以减少功放的切换损耗。基于滞环比较思想在DSM中提出了一种可变门限量化策略,并通过理论和仿真分析了该策略下DSM输出的平均切换速率以及带内SNR性能。结果表明,采用所提出的量化策略,在带内SNR减少有限的情况下,能够有效降低DSM输出的平均切换频率。     

基于多比特带通△∑调制器的射频数字功放

为提高射频功放的线性和效率,提出了一种基于多比特带通△∑调制器(BPDSM)的射频数字功放结构并给出了BPDSM的设计方法。针对调制器CRFB实现结构中关键路径过长的问题,利用重定时、流水线和超前计算等技术对实现结构进行了改进,将BPDSM的实现速率提高至200 MHz。提出了多电平开关功放的电路结构,将多个具有独立电源的开关功放单元进行串联,实现了对BPDSM输出多比特脉冲信号的高效开关放大。最后,利用FPGA器件及分立元件实现了频率为30 MHz的数字功放,输出功率为10 W时效率达到60%。     

记忆非线性功率放大器的高效预失真

记忆非线性放大器的预失真问题一直是预失真技术的难点。通常采用Volterra级数、Hammerstein模型和神经网络等模型的记忆预失真都存在形式复杂、自适应困难的缺点。文章通过增加两个延时环节将基于多项式的无记忆放大器的高效预失真结构推广到有记忆放大器的预失真中,并联合一种简单的带抽头延时的非线性多项式模型作为记忆预失真器模型实现了记忆非线性放大器的快速、高效的线性化。仿真结果表明,利用所提出的预失真方案能快速实现记忆放大器的预失真,而且显著提高了线性化性能。     

Application of principal component analysis based effective digital predistortion technique for low‐cost FPGA implementation

This article investigates the issue of low‐cost digital predistortion (DPD) implementation in fixed‐point field programmable gate array (FPGA) by considering the bit‐resolution along with lower number of coefficients. The impact of principle component analysis (PCA) on bit‐resolution of DPD solution is proposed within the context of established DPD models. Unlike previously proposed PCA based solutions, it is established by simulation and measurement that the numerical stability problem associated with popular models such as memory polynomial (MP) can be alleviated when PCA is applied to the observation data matrix. It is reported with measurement results that PCA based model provides better linearization performance with the least memory size requirement and number of LUTs in 16‐bit fixed‐point FPGA operation than MP, orthogonal memory polynomial (OMP), and generalized memory polynomial (GMP) models. The performance of the proposed model, is evaluated in terms of normalized mean square error, adjacent channel error power ratio, matrix condition number, and dispersion coefficient for continuous Class‐AB and ZX60‐V63+ power amplifiers using wide code‐division multiple access signal (WCDMA) and long term evolution (LTE) signal with peak‐to‐average‐power ratio (PAPR) around 9.895 and 11.92 dB, respectively.     

One‐bit in‐phase observation for direct learning‐based digital predistortion with modified frequency‐domain delay estimation and alignment

This article proposes a novel digital predistortion (DPD) implementation method for RF power amplifiers. The new approach adopts only one 1‐bit comparator in the feedback path to observe the in‐phase (I) or the quadrature (Q) component of the error signal between the input and the output signals. To this end, the theoretical derivation of the in‐phase observation based on direct learning architecture (DLA) DPD is first given in this article, by combining the existing 1‐bit method and the low‐cost in‐phase observation. To facilitate the delay estimation and alignment, a modified iterative frequency‐domain delay estimation is presented, which only acquires either I or Q components of the output signal to achieve satisfied delay estimation. Experimental results show that the proposed DPD method decreased the normalized mean square error (NMSE) and the adjacent channel power ratio (ACPR) to less than ?42 and ?51 dB, respectively, which indicates that the proposed DPD system can achieve comparable performance as the existing DPD identification techniques with lower implementation complexity.     

数字基带预失真系统中环路延迟估计的FPGA实现

基于FPGA芯片Stratix Ⅱ EP2S60F672C4设计实现了数字基带预失真系统中的环路延迟估计模块.该模块运用了一种环路延迟估计新方法,易于FPGA实现.同时,在信号失真的情况下也能给出正确的估计结果.Modelsim SE 6.5c的时序仿真结果和SignalTaps Ⅱ的硬件调试结果验证了模块的有效性.     

压缩感知框架下宽带功放预失真模型

射频功放的非线性特性是一个重要的研究方向,针对预失真系统采样率过高的问题,提出一种新的宽带功放预失真模型,即在反馈回路采用基于正弦调频(SFM)信号的调制宽带解调(MWC)对信号进行采样,再用变步长广义自适应匹配追踪(VS-GSAMP)算法对信号进行重构,降低反馈回路采样速率,提升线性化效果。实验结果表明,在提高信号重构精度的同时,NSME(normalized mean squared error)显示较MP、GMP模型提升了2~3 d B,ACPR(adjacent channel power radio)约改善了21 d B,该方法能够使系统在较低的采样率下获得良好的线性性能。     

基于支持向量机的记忆功率放大器预失真

提出了一种新的针对记忆非线性功率放大器的支持向量机（SVM）预失真器。通过对其建模中采用径向基核函数和多项式核函数所表现出的性能特点进行分析,为核函数的选取提供了参考。采用以多项式为核函数的SVM对3种典型的记忆非线性功率放大器模型进行线性化仿真,结果表明了该方法的有效性和鲁棒性。     

Adaptive predistortion using threshold decomposition‐based piecewise linear modeling

A new adaptive predistortion approach for nonlinear power amplifiers based on the piecewise linear (PWL) approximation of nonlinear functions is presented. The PWL model is obtained using threshold decomposition (TD) of the input‐output characteristics. The TD based PWL model is used to develop a baseband predistorter using both the direct and the indirect learning architectures. The proposed predistorter is proved to provide a better performance in suppressing nonlinear distortion than conventional polynomial predistorters and a reduced hardware complexity as compared to lookup table (LUT) approach. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

稀疏的归一化功放模型及预失真应用*

针对射频功放的非线性特性进行了研究,提出一种新的稀疏化的Volterra级数模型。该模型基于压缩感知算法,将稀疏系统的辨识等效为信号的重构问题,利用正则正交匹配（ROMP）算法对核系数进行稀疏化并选择出活跃的核系数。将提出的模型与记忆多项式（MP）模型、通用记忆多项式（GMP）模型进行比较,较MP模型的建模精度提升10.7dB,模型系数减少25%,较GMP模型的建模精度提升3.9dB,但模型系数减少84.58%。仿真结果表明：提出的方法实现良好的预失真线性化性能,极大地降低模型系数,优于传统的功放行为模型。由此验证对功放的线性化技术发展具有参考价值。     

基于动态有理函数的功放模型及预失真应用

针对现代无线通信系统中射频功率放大器的非线性与记忆效应,提出一种新的低复杂度的动态有理函数模型,该模型简化了有理函数模型,通过两个多项式的比进行建模,但分子是包络记忆多项式的形式,分母由无记忆多项式构成.通过模型仿真和预失真应用系统验证,结果表明:与记忆多项式模型相比,动态有理函数模型所需的系数要少30.6％,模型精度却与其相近,邻信道功率比(ACPR)改善约20 dB,而与有理函数模型相比,所需系数要少21.9％,模型精度改善2.4 dB,ACPR改善约15 dB.由此证明了该模型在复杂度和精确度上的优越性,对功放预失真的研究具有重要的参考价值.