An ultralow-loss and broadband micromachined RF inductor for RFIC input-matching applications

In this brief, we demonstrate that ultralow-loss and broadband inductors can be obtained by using the CMOS process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the inductors. The results show that a 378.5% increase in maximum Q-factor (Q/sub max/) (from 10.7 at 4.7 GHz to 51.2 at 14.9 GHz), a 22.1% increase in self-resonant frequency (f/sub SR/) (from 16.5 to 20.15 GHz), a 16.3% increase (from 0.86 to 0.9999) in maximum available power gain (G/sub Amax/) at 5 GHz, and a 0.654-dB reduction (from 0.654 dB to 4.08/spl times/10/sup -4/ dB) in minimum noise figure (NF/sub min/) at 5 GHz were achieved for a 2-nH inductor after the backside ICP dry etching. In addition, state-of-the-art ultralow-loss G/sub Amax//spl les/0.99 (i.e., NF/sub min//spl les/0.045 dB) for frequencies lower than 12.5 GHz was achieved for this 2-nH inductor after the backside inductively coupled-plasma dry etching. This means this on-chip inductor-on-air can be used to realize an ultralow-noise 3.1-10.6 GHz ultrawide-band RFIC. These results show that the CMOS process compatible backside ICP etching technique is very promising for system-on-a-chip applications.     

一种应用于6-9GHz UWB系统的低噪声CMOS射频前端设计

本文介绍了一种应用于6-9 GHz超宽带系统的全集成差分CMOS射频前端电路设计。在该前端电路中应用了一种电阻负反馈形式的低噪声放大器和IQ两路合并结构的增益可变的折叠式正交混频器。芯片通过TSMC 0.13µm RF CMOS工艺流片,含ESD保护电路。经测试得该前端电路大电压增益为23~26dB,小电压增益为16~19dB;大增益下前端电路平均噪声系数为3.3-4.6dB,小增益下的带内输入三阶交调量(IIP3)为-12.6dBm。在1.2V电压下,消耗的总电流约为17mA。     

A low noise CMOS RF front-end for UWB 6-9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in th...     

A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier(LNA),a broadband active balun,a high linearity mixer and a bandgap reference(BGR) circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched cap...     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。     

一种高效率的适合于低功耗应用的电荷泵电路

设计实现了一种高效率的电荷泵电路。利用电容和晶体管对电荷传输开关进行偏置来消除开关管阈值电压的影响。同时,通过对开关管的的衬底进行动态的偏置使得在电荷传输期间当开关管打开时其阈值电压较低,在开关管关断时其阈值电压较高。该电荷泵电路的效率得到了提高。基于0.18μm,3.3V标准CMOS工艺实现了该电路。在每级电容为0.5pF,时钟频率为780KHz,电源电压为2V的情况下,测得的8级电荷泵的输出电压为9.8V。电荷泵电路和时钟驱动电路从电源处总共消耗了2.9μA的电流。该电荷泵电路适合于低功耗的应用。     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

Current-mode cyclic ADC for low power and high speed applications

A new current-mode cyclic ADC is proposed. An 8 bit ADC is fabricated and fully tested. The experimental results are summarised and compared with other schemes. This ADC enables a conversion time less than 10 mu s with clock frequency of 450 kHz to be obtained. The proposed ADC is found to be useful where the power and size are crucial requirements.<>     

A complete RF power technology assessment for military applications

During many years, the French MOD has supported technology developments and specific MMICs designs for power amplification from S-band to Ku-band, for radar and electronic warfare applications. Due to critical issues at system level, an independent assessment made in a governmental laboratory was required by program officers in order to check all the key parameters of a new technology. The objective of this paper is to present and analyse data obtained on a PPHEMT technology, simultaneously taking into account technology, microwave measurements and reliability issues. The originality of this work is to gather all these aspects, combined by a new RF life test bench with negative and positive temperatures environment.     

Linearity and power characteristics of SiGe HBTs at high temperatures for RF applications

In this paper, the power gain, power-added efficiency (PAE) and linearity of power SiGe heterojunction-bipolar transistors at various temperatures have been presented. The power characteristics were measured using a two-tone load-pull system. For transistors biased with fixed base voltage, the small-signal power gain and PAE of the devices increase with increasing temperature at low base voltages, while they decrease at high base voltages. Besides, the linearity is improved at high temperature for all voltage biases. However, for devices with fixed collector current, the small-signal power gain, PAE, and linearity are nearly unchanged with temperature. The temperature dependence of power and linearity characteristics can be understood by analyzing the cutoff frequency, the collector current, Kirk effect and nonlinearities of transconductance at different temperatures.     

应用于超宽带系统中的低功耗、高速FFT/IFFT处理器设计

设计了一种应用于超宽带(UWB)无线通信系统中的FFT/IFFT处理器.采用8×8×2混合基算法进行FFT运算,实现了2路64点或者1路128点FFT功能,并为该算法提出了一种新型的8路并行反馈结构.该结构提高了处理器的数据吞吐率,降低了芯片功耗.为了减少处理器中的乘法数目,提高时序性能,提出了改进型移位加算法.设计的FFT/IFFT处理器采用SMIC 0.13μm CMOS工艺制造,芯片的核心面积为1.44mm2.测试结果表明,该芯片最高数据吞吐率到达1Gsample/s,在典型的工作频率500Msample/s下,芯片功耗为39.6mW.与现有同类型FFT芯片相比,该芯片面积缩小了40%,功耗减少了45%.     

Ultra-low power LNA design technique for UWB applications

In this paper, a design technique to improve low noise amplifier (LNA) performance is proposed. This technique is based on a new operating parameter (OP) of MOSFETs for radio frequency (RF) applications. This technique is used to optimize low noise amplifier (LNA) parameters for Ultra-Wideband (UWB) applications. The presented methodology predicts the optimum biasing point to maximize LNA performance. Simulation results show that the proposed methodology can increase the figure of merit (FoM) by 70% compared to traditional methodologies, without having a significant effect on either noise figure (NF) or linearity characteristics.     

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>     

一种应用于双载波正交频分复用的超宽带单片射频收发机

本文给出了一种用于双载波正交频分复用的超宽带单片射频收发机芯片。该芯片采用直接变频结构,片内共集成了两路接收机,两路发射机,一个双载波频率综合器并提供控制收发机工作状态的三线串行接口。此芯片使用台积电 0.13 微米射频CMOS工艺制造,尺寸为 4.5mmx3.6mm。测试结果表明：该收发机的接收机链路噪声系数为 5~6.2dB,最大增益为 78~84dB,可变增益为 64dB,带内和带外三阶交调点分别为-6dBm和 4dBm,在所有频带上都获得良好的输入匹配（S11<-10）;该收发机的发射机最大可输出-5dBm 功率,带内主要杂散均小于 -33dBc（镜像抑制<-33dBc,载波泄露<-34dBc）,典型的输出三阶交调点为 6dBm;该收发机的双载波频率综合器可以同时输出两路频率可独立配置的载波信号,其跳频时间小于1.2ns。在1.2V单电源供电下,整个射频芯片消耗最大电流为420mA。     

A fully integrated low power PAM multi-channel UWB transmitter

A new transmitter for ultra-wideband (UWB) impulse radio is described in this paper. The new UWB transmitter implements a low power Gaussian shaping filter to reduce the side-lobe in the frequency domain. A simple pulse amplitude modulation (PAM) circuit is used to keep the power consumption low. The proposed architecture features the simple design, low-power operation, and enables the pulse-shape generation for a multi-channel UWB. The core layout size is only 0.2 mm². The simulation results show that the generated signals satisfy the FCC spectrum mask, and the average power consumption is <1.97 mW for the 1.8 V supply voltage. Pulses are transmitted at a PRF (pulse repetition frequency) of 40.5 MHz in 500 MHz bandwidth channels equally spaced within the 3.1–10.6 GHz UWB. This transmitter is designed and fabricated in a 0.18-μm CMOS process.     

Optimizing RF front ends for low power

This paper discusses optimizations for the power dissipation of RF front ends in portable wireless devices. A breakthrough in power dissipation can be achieved by simultaneously optimizing the antenna interface, circuits, and IC technology of such devices. A model that predicts the minimum power dissipation of a front end for both short-range and long-range connections will be introduced. Using these models, the impact of the antenna interface on the power dissipation will be assessed. Using two antennas with equal gain combining, a typical power dissipation reduction of 2.5 to 30 times can be achieved. Using high-impedance circuits for short-range systems in combination with silicon-on-anything technology, a further reduction of power dissipation by up to one order of magnitude can be realized     

高功率低损耗六路功分器的设计与分析

针对高功率微波对功率放大器轻重量和小体积的要求,采用基于功率分配合成技术中的同相叠加原理,设计了一种C波段的结构紧凑型窄带6路功率分配器。该分配器通过射频同轴N型连接器输入射频信号,通过环形无氧铜窄带线等相均分为6路。利用CST软件对该器件进行了初步结构优化设计和S-parameter模拟仿真,理论传输系数为-7.78 dB。结果表明,该器件能承受5.0~5.3 GHz的工作频率,功率容量达到1 000 W,各端口的功率传输效率达到97.5%以上,插入损耗为0.2 dB以内,完全可以满足使用要求。     

A low-complexity UWB RF receiver based on a novel low noise amplifier

A novel low-complexity ultra-wideband UWB receiver is proposed for short-range wireless transmission communications without considering multipath effect. The receiver chip uses a low-complexity UWB non-coherent receiving system solution with the core module composed of squarer and low-pass filter. By introducing asymmetric gate series inductance and RCL parallel negative feedback loop into the two-stage push–pull amplifier, the low-noise amplification and input impedance matching at ultra-wide bandwidth were achieved. With only two inductors and self-biased function, the chip area and power consumption can be saved largely. The proposed UWB receiver chip was fabricated in a 0.18 μm RF CMOS technology. Experimental results show that it can achieve a bandwidth of 3–5 GHz, maximum receiving symbol rate of 250 Mbps, receiving sensitivity of −80 dBm and power consumption of 36 mW, providing a low-complexity and high-speed physical implementation of the short-range high-speed wireless interconnection between electronic devices in the future.     

Active inductor based tunable multiband RF front end design for UWB applications

This study describes a new and simple frequency compensation for three stages amplifiers based on revered nested Miller compensation (RNMC) structure. Using only one and small compensation capacitor reduced circuit complexity and die area while shows better performance compared to RNMC. Also the proposed method is unconditional stable due to cancellation of second dominant pole by a zero. Ample simulations are performed using HSPICE and TSMC 0.18 µm CMOS technology to verify robustness of presented circuit. Simulation results show 114 dB, 6.66 MHz and 360 µW as DC gain, GBW and power consumption respectively.