A latch phenomenon in buried N-body SOI NMOSFET's

The authors show that a snapback effect resulting in a latching can exist in a buried N-body NMOS device on silicon-on-insulator (SOI). Using numerical simulations, it is demonstrated that when V_GS is less than the flat-band voltage and after triggering, this kind of device behaves as a floating-base n-p-n bipolar transistor, the base hole density of which is controlled by an inversion layer instead of the usual base doping. The latch phenomenon results from the combination of this parasitic quasi-bipolar device, a back surface NMOS transistor, and impact ionization current     

PMOS input merged bipolar/sidewall MOS transistors (PBiMOStransistors)

A concept of merging vertical n-p-n bipolar and sidewall PMOS transistors into merged PBiMOS transistors is described. This concept allows device structures which perform more complex functions to be integrated into a given area. The feasibility of this concept is demonstrated by fabricating and DC characterizing PBiMOS transistor structures which occupy ~1.1 times the area of a single n-p-n bipolar transistor. The PMOS sidewall transistor characterization results suggest that a reasonable control of the key device parameters may be achieved. These results also suggest that, for the 23-nm gate oxide thickness, the doping requirements for the n^- collector of the n-p-n bipolar and the channel of the sidewall PMOS transistors are similar     

A high-performance lateral bipolar transistor fabricated on SIMOX

Double-diffused, lateral n-p-n bipolar transistors were fabricated in a simple CMOS-like process using SIMOX silicon-on-insulator (SOI) substrates. Excellent device characteristics were achieved, with peak h_FE=120, BV_CEO=10 V, and peak f_t=4.5 GHz. The f_t versus BV _CEO trade-off was studied as a function of n ^- collector width. f_t>25 GHz is predicted for this structure with an improved device layout and optimized basewidth. This process may be easily extended in order to fabricate complementary BJTs in a C-BiCMOS thin-film SOI technology     

Co-integration of resonant tunneling and double heterojunctionbipolar transistors on InP

The authors report the first co-integration of resonant tunneling and heterojunction bipolar transistors. Both transistors are produced from a single epitaxial growth by metalorganic molecular beam epitaxy, on InP substrates. The fabrication process yields 9-μm²-emitter resonant tunneling bipolar transistors (RTBTs) operating at room temperature with peak-to-valley current ratios (PVRs) in the common-emitter transistor configuration, exceeding 70, at a resonant peak current density of 10 kA/cm², and a differential current gain at resonance of 19. The breakdown voltage of the In_0.53Ga_0.47As-InP base/collector junction, V_CBO, is 4.2 V, which is sufficient for logic function demonstrations. Co-integrated 9-μm²-emitter double heterojunction bipolar transistors (DHBTs) with low collector/emitter offset voltage, 200 mV, and DC current gain as high as 32 are also obtained. On-wafer S-parameter measurements of the current gain cutoff frequency (f_T) and the maximum frequency of oscillation (f_max) yielded f _T and f_max values of 11 and 21 GHz for the RTBT and 59 and 43 GHz for the HBT, respectively     

Digital characteristics of CMOS devices at cryogenic temperatures

The results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and of supply voltage between 3 and 20 V are presented. Using a fixed supply of 5 V, the low noise margin decreased from 2.54 to 2.11 V, but the high noise margin increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V_II and V_IH increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity. V _H-V_I, and V_IH-V _II all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the β_N/β_P ratio as the temperature is lowered     

The effect of substrate bias on hot-carrier damage in NMOS devices

Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V_d =8 V and V_g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V_b), having a power-law gradient of 0.5 for V_b=0 V and 0.3 for V_b=-9 V. Investigation of the type of damage resulting from stressing shows that at V_b=0 V, interface state generation results, while at V_b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions     

A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process     

An AlGaAs/GaAs heterostructure-emitter bipolar transistor

An AlGaAs/GaAs heterostructure-emitter bipolar transistor using separate carrier injection and confinement is discussed. A common-emitter current gain of 28 with BV_CEO=15 V was obtained at a base doping level of 1×10¹⁹/cm³ . No spacer layer was inserted in the structure. This transistor combines the merits of homojunction transistors and regular heterostructure bipolar transistors (HBTs) and is simple to fabricate     

An InAs channel heterojunction field-effect transistor with hightransconductance

A report is presented on an InAs channel field-effect transistor (FET) based on AlGaSb/InAs/AlSb/AlGaSb structures grown by molecular-beam epitaxy. Excellent pinch-off characteristics have been obtained. An FET with a gate length of 1.7 μm showed transconductances ranging from 460 mS/mm (at V_ds=0.5 V) to 509 mS/mm (at V_ds=1 V) and a K factor of 1450 mS/Vmm (at V_ds=1 V) at room temperature     

Fabrication and characterization of the amorphous-silicon staticinduction transistor

Experimental results for the fabrication and electrical characterization of a hydrogenated amorphous silicon static induction transistor are reported. The I-V measurements demonstrate the triode-like enhancement mode operation of the device and show an on-off current ratio of 300 and a pinchoff voltage of -9.5 V for V_ds=6 V. Numerical simulation suggests that the differences between experimental and theoretically predicted results are due to the presence of a high-density-of-states layer at the a-Si:H/a-Si:H interface     

High-frequency InP/InGaAs double heterojunction bipolar transistorson Si substrate

Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I_C=15 mA, f _T was 59 GHz at V_CE=1.8 V, and f _max was 69 GHz at V_CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V_CE of 3.8 V was applied for I_C=7.5 mA in the S-parameter measurements to give an f_T of 39 GHz and an f_max of 52 GHz     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

A high-speed, small-area, threshold-voltage-mismatch compensationsense amplifier for gigabit-scale DRAM arrays

A high-speed small-area DRAM sense amplifier with a threshold-voltage (V_T) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V_T mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V_T mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays     

Experimental determination of self-heating in submicrometer MOStransistors operated in a liquid-helium ambient

Self-heating (SH) in submicrometer CMOS transistors operated at liquid-helium temperature and under different bias conditions was experimentally verified by measuring the temperature T_Si in the proximity of the device. T_Si was measured by using a silicon resistor, placed in the same bulk nearby the device under test, as a temperature sensor. It was found that the heat generated by the NMOS transistor of a CMOS inverter structure penetrates deep into the substrate and reduces very strongly the n-well impedance, giving rise to large variations in the kink of the I_drain -V_drain characteristics of the neighbor PMOS transistor. Experimental results confirm that SH must not be underestimated when characterizing and modeling low-temperature device operation     

1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

Current gain-Early voltage products in heterojunction bipolartransistors with nonuniform base bandgaps

The tradeoff between common-emitter current gain (β) and Early voltage (V_A) in heterojunction bipolar transistors (HBTs) where the bandgap varies across the base has been studied. The Early voltage depends exponentially on the difference between the bandgap at the collector side of the base and the largest bandgap in the base, allowing very high Early voltages with only very thin narrow bandgap regions. Using Si/Si_1-xGe_x/Si HBTs with a two-layer stepped base, βV_A products of over 100000 V have been achieved for devices with a cutoff frequency expected to be about 30 GHz     

Bipolar transistor fabrication using selective epitaxial growth ofP- and B-doped layers in gas-source Si molecular beam epitaxy

Si n-p-n bipolar transistor fabrication using selective epitaxial growth in disilane gas-source Si molecular beam epitaxy (Si-MBE) is discussed. Selective growth of B-doped and P-doped Si was used for the base- and emitter-layer formation, respectively. The growth temperature was 600°C. No ion-implantation process was used. The base ohmic contact was formed using Al selective chemical vapor deposition. The fabricated transistor showed normal emitter-base and base-collector I-V characteristics. The common-emitter characteristics revealed a maximum current gain of 30     

1.0-µm n-well CMOS/bipolar technology

High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-µm CMOS with a new "hot carrier resistant" self-defined polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors, it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n⁺-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n⁺-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

Self-aligned SiGe-base heterojunction bipolar transistor byselective epitaxy emitter window (SEEW) technology

In the device a SiGe epitaxial base is integrated in a structure which uses in situ doped epitaxial lateral overgrowth for the formation of the emitter window and the extrinsic base contact. Nearly ideal I -V characteristics have been achieved for a base width of 60 nm with an intrinsic base resistance of 4.6 kΩ/□ and for emitter widths down to 0.4 μm. A DC collector current enhancement factor of 3.1 was obtained relative to a Si homojunction transistor with a 1.25 times higher intrinsic base resistance. The breakdown voltage BV_CBO is identical for both Si and SiGe devices, even though the collector-base depletion region is partly overlapped with the reduced-bandgap SiGe strained layer. The lower BV_CEO, measured for the SiGe-base transistor, is due to the higher current gain. Based on these results the fabrication of high-speed bipolar circuits that take advantage of SiGe-base bandgap engineering seems possible using selective epitaxy emitter window (SEEW) technology     

BiMOS transistors: merged bipolar/sidewall MOS transistors

The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible