Characterization of oxide traps in 0.15 μm MOSFETs using random telegraph signals

Random telegraph signals (RTS) have been used to characterize oxide traps of W×L=0.97×0.15 μm² medium-doped drain n-MOSFETs. RTS have been measured in the linear and saturation regions of operation, both in forward and reverse modes where the drain and source are reversed. The contribution of mobility fluctuations as well as number fluctuations to the amplitude of RTS has been investigated. The scattering coefficient due to screened Coulomb scattering effect is computed from the measured data as a function of channel carrier density. The depth of the position of the trap in the oxide from Si–SiO₂ interface is calculated utilizing the dependence of the emission and capture times on the gate voltage. In addition, the position of the trap along the channel with respect to the source is obtained using the difference in the drain voltage dependence of the capture and emission times between the forward and reverse modes. Knowing the location of the trap in the oxide and along the channel, the energy associated with the trap can be extracted accurately from the data. This technique allows one to evaluate the trap energy at the point where the trap is located without any assumptions about the location of the trap or the need for variable temperature measurements. The probed trap was found to be an acceptor type center (repulsive for an n-MOSFET) located at about 27 Å deep the oxide, half-way between drain and source with an energy of E_Cox−E_T=3.04 eV, slightly above the conduction band edge.     

Extraction of interface states at emitter–base heterojunctions in AlGaAs/GaAs heterostructure bipolar transistors using sub-bandgap photonic excitation

Distribution of interface states at the emitter–base heterojunctions in heterostructure bipolar transistors (HBTs) is characterized by using current–voltage characteristics using sub-bandgap photonic excitation. Sub-bandgap photonic source with a photon energy E_ph which is less than the energy bandgap E_g (E_g,GaAs = 1.42, E_g,AlGaAs = 1.76 eV) of emitter, base, and collector of HBTs, is employed for exclusive excitation of carriers only from the interface states in the photo-responsive energy range at emitter–base heterointerface. The proposed method is applied to an Al_0.3Ga_0.7As/GaAs HBT (A_E = W_E × L_E = 250 × 100 μm²) with E_ph = 0.943 eV and P_opt = 3 mW. Extracted interface trap density D_it was observed to be D_it,max  4.2 × 10¹² eV⁻¹ cm⁻² at emitter–base heterointerface.     

Charge trapping and interface states in hydrogen annealed HfO2–Si structures

Metal–oxide–semiconductor (MOS) capacitors based on HfO₂ gate stacks with Al and TiN gates are compared to study the effect of the gate electrode material to the properties of insulator–semiconductor interface. The structures under study were shown to contain interface trap densities of around 2 × 10¹¹ cm⁻² eV⁻¹ for Al gate and up to 5.5 × 10¹² cm⁻² eV⁻¹ for TiN gate. The peak in the surface state distribution was found at 0.19 eV above the valence band edge for Al electrode. The respective capture cross-section is 6 × 10⁻¹⁷ cm² at 200 K.The charge injection experiments have revealed the presence of hole traps inside the dielectric layer. The Al-gate structure contains traps with effective capture cross-section of 1 × 10⁻²⁰ cm², and there are two types of traps in the TiN-gate structure with cross-sections of 3.5 × 10⁻¹⁹ and 1 × 10⁻²⁰ cm². Trap concentration in the structure with Al electrode was considerably lower than in the structure with TiN electrode.     

Silicon-based optical receivers in BiCMOS technology for advanced optoelectronic integrated circuits

A double photodiode (DPD) and a phototransistor were implemented in an industrial 0.8 μm bipolar complementary metal oxide semiconductor (BiCMOS) n-well process. Both devices are 100% BiCMOS compatible, so that no process modifications were necessary. A −3 dB bandwidth of more than 200 MHz was measured for the DPD. The rise and fall times of the photodiode are less than 1 ns. By an optimized antireflection coating layer for a wavelength of 638 nm a quantum efficiency of η=95%, which corresponds to a responsivity of R=0.49 A/W, is achievable. A phototransistor with a light-sensitive area of 53×53 μm² was developed. Its current amplification of B=300 results in a much larger responsivity compared to the photodiodes. Measurements have shown a −3 dB bandwidth of 7.8 MHz for the phototransistor.     

Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials

Metal-oxide-semiconductor capacitors based on HfO₂ gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator–semiconductor interface.C–V and G–ω measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180–300 K. From the maximum of the plot G/ω vs. ln(ω) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge.The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2×10¹¹ cm⁻²eV⁻¹ for Al and up to (3.5–5.5)×10¹² cm⁻² eV⁻¹ for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8×10⁻¹⁷ cm² at 200 K for Al–HfO₂–Si structure.     

Dynamic hot-carrier induced degradation in n-channel polysilicon thin-film transistors

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.     

High breakdown voltage Schottky rectifier fabricated on bulk n-GaN substrate

Vertical Schottky rectifiers have been fabricated on a free-standing n-GaN substrate. Circular Pt Schottky contacts with different diameters (50 μm, 150 μm and 300 μm) were prepared on the Ga-face and full backside ohmic contact was prepared on the N-face by using Ti/Al. The electron concentration of the substrate was as low as 7 × 10¹⁵ cm⁻³. Without epitaxial layer and edge termination scheme, the reverse breakdown voltages (V_B) as high as 630 V and 600 V were achieved for 50 μm and 150 μm diameter rectifiers, respectively. For larger diameter (300 μm) rectifiers, V_B dropped to 260 V. The forward turn-on voltage (V_F) for the 50 μm diameter rectifiers was 1.2 V at the current density of 100 A/cm², and the on-state resistance (R_on) was 2.2 mΩ cm², producing a figure-of-merit (V_B)²/R_on of 180 MW cm⁻². At 10 V bias, forward currents of 0.5 A and 0.8 A were obtained for 150 μm and 300 μm diameter rectifiers, respectively. The devices exhibited an ultrafast reverse recovery characteristics, with the reverse recovery time shorter than 20 ns.     

Fabrication and characterization of air-stable, ambipolar heterojunction-based organic light-emitting field-effect transistors

We present our first application of the neutral cluster beam deposition (NCBD) method to fabricate bilayer heterojunction-based organic light-emitting field-effect transistors (OLEFETs) by superimposing two layers of α,ω-dihexylsexithiophene (DH6T) and N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13) successively. Based upon well-balanced ambipolarity (hole and electron field-effect mobilities of 2.22 × 10⁻² and 2.78 × 10⁻² cm²/Vs), the air-stable OLEFETs have demonstrated good field-effect characteristics, stress-free operational stability and electroluminescence under ambient condition.     

Luminescence and microstructure of Er/O co-doped Si structures grown by MBE using Er and SiO evaporation

Er and O co-doped Si structures have been prepared using molecular-beam epitaxy (MBE) with fluxes of Er and O obtained from Er and silicon monoxide (SiO) evaporation in high-temperature cells. The incorporation of Er and O has been studied for concentrations of up to 2×10²⁰ and 1×10²¹ cm⁻³, respectively. Surface segregation of Er can take place, but with O co-doping the segregation is suppressed and Er-doped layers without any indication of surface segregation can be prepared. Si_1−xGe_x and Si_1−yC_y layers doped with Er/O during growth at different substrate temperatures show more defects than corresponding Si layers. Strong emission at 1.54 μm associated with the intra-4f transition of Er³⁺ ions is observed in electroluminescence (EL) at room temperature in reverse-biased p–i–n-junctions. To optimize the EL intensity we have varied the Er/O ratio and the temperature during growth of the Er/O-doped layer. Using an Er-concentration of around 1×10²⁰ cm⁻³ we find that Er/O ratios of 1 : 2 or 1 : 4 give higher intensity than 1 : 1 while the stability with respect to breakdown is reduced for the highest used O concentrations. For increasing growth temperatures in the range 400–575°C there is an increase in the EL intensity. A positive effect of post-annealing on the photoluminescence intensity has also been observed.     

Effects of quantization on random telegraph signals observed in deep-submicron MOSFETs

Random telegraph signals (RTS) have been investigated in the drain to source voltage of W_eff×L_eff=1.37×0.17 μm² medium-doped drain (MDD) n-type MOSFETs. The emission (τ_e) and capture (τ_c) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τ_e and τ_c including the influence of bulk bias (V_SB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO₂ interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔV_DS/V_DS) shows a positive dependence on V_SB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.     

On the geometrical dependence of low-frequency noise in SiGe HBTs

We present an investigation of the dependence of low-frequency noise on device geometry in advanced npn silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs). The devices examined in this work have fixed emitter width (W_E = 0.4 μm), but varying emitter length (0.5 μm  L_E  20.0 μm), and thus the ratio of the emitter perimeter (P_E) to the emitter area (A_E) varies widely, making it ideal for examining geometrical effects. The SPICE noise parameter A_F extracted from these devices decreases with increasing L_E. Furthermore, the low-frequency noise measured on SiGe HBTs with significantly different P_E/A_E ratios suggests a possibility that the fundamental noise source for the diffusion base current may be located at the emitter periphery. Transistors with different distances between the emitter edge and the shallow trench edge (XEC), and shallow trench edge to deep trench edge (XTC), are also investigated. The SiGe HBTs with a smaller value of XEC have higher low-frequency noise, but no significant difference is found in devices with varying XTC. Explanations of the observed noise behavior are suggested.     

Investigation of relation between intermetallic and tin whisker growths under ambient condition

The relation between the whisker growth and intermetallic on various lead-free finish materials that have been stored at ambient condition for 2 yrs (6.3 × 10⁷ s) is investigated. The matte Sn plated leadframe (LF) had the needle-shaped whisker and the nodule-shaped whisker was observed on the semi-bright Sn plated LF. Both the Sn plated LFs had a same columnar grain structure and both whiskers were grown in connection with the scalloped intermetallic compound (IMC) layer. The morphology of the IMC layer is similar, regardless of the area which has whisker or not. On the Sn–Bi finish and bright Sn plated LF, hillock-shaped and sparsely grown branch-shaped whiskers were observed, respectively. The IMC grew irregularly under both the areas with or without whisker. The IMC growth along the Sn grain boundaries generated inner compressive stress at the plating layer. Atomic force microscopy (AFM) profiling analysis is useful for characterization the IMC growth on the Sn and Cu interface. The measured root mean square (RMS) values IMC roughness on semi-bright Sn, matte Sn, and bright Sn plated LF were 1.82 μm, 1.46 μm, and 0.63 μm, respectively. However, there is no direct relation between whisker growth and the RMS value. Two layers of η′-Cu₆Sn₅ were observed using field emission transmission electron microscopy (FE-TEM): fine grains and coarse grains existed over the fine grains.     

Charge trapping characterization of MOCVD HfO2/p-Si interfaces at cryogenic temperatures

The paper focuses on the study of charge trapping processes in high-k MOS structures at cryogenic temperatures. It was shown, that there is extremely strong trapping in shallow electron and hole traps, localized in the high-k dielectrics. Concentration of shallow electron traps is as much as 10¹³ cm⁻², while abnormal small capture cross-sections (4.5–8 × 10⁻²⁴ cm² for different samples, accordingly) suggests localization of shallow emitting electron traps in transition layer “high-k dielectric/Si”, more, than at the interface. Shallow hole traps with concentration near 10¹² cm⁻² are separated from silicon valence band with energy barrier in the range 10–39 meV for different samples.     

Silicon oxynitride integrated waveguide for on-chip optical interconnects applications

This work explores the microfabrication technology for realizing miniature waveguide structure for on-chip optical interconnects applications. Thick oxynitride films were prepared by plasma enhanced chemical vapor deposition (PECVD) with N₂O, NH₃ and SiH₄ precursors. The composition and the bonding structure of the oxynitride films were investigated with Fourier transform infrared spectroscopy (FTIR), X-ray photoelectron spectroscopy (XPS), and secondary ion mass spectroscopy. Results showed that the silicon oxynitride deposited with gas flow rates of NH₃/N₂O/SiH₄ = 10/400/10 (sccm) has favorable properties for integrated waveguide applications. The refractive index of this layer is about 1.5 and the layer has comparative low densities of O–H and N–H bonds. The hydrogen bonds can be further eliminated with high temperature annealing of the as-deposited film in nitrogen ambient and the propagation loss can be reduced significantly with thermal annealing. An integrated miniature waveguide with cross-section of 2 μm × 3 μm was realized with the proposed technology. The waveguide is able to transmit signal in either TE or TM mode with propagation loss <0.6 dB/cm (at 1550 nm) and bending radius of about 6 μm.     

Fabrication of suspended thin film resonator for application of RF bandpass filter

Characteristics of AlN thin film and thin film resonator for RF bandpass filter have been studied. AlN thin films were deposited by RF magnetron sputter system. Deposition parameters such as N₂ contents, Ar and N₂ partial pressures, and the distance between metal target and substrate were found to affect the piezoelectric response. To fabricate the suspended thin film resonator (STFR) using the piezoelectric AlN thin film, the etching of AlN and the surface micromachining process were conducted. The thickness of AlN film and membrane for the STFR are 2 and 15 μm, respectively. This membrane was fabricated by SOI technology. The device with the dimension of 160 × 160 μm² has a resonant frequency of 1.653 GHz, a K_eff² of 2.4%, a bandwidth of 17 MHz, and a quality factor of 91.7. The device with the dimension of 200 × 200 μm² has a resonant frequency of 1.641 GHz, a K_eff² of 1.2%, and a bandwidth of 9 MHz, and a quality factor of 50.2.     

Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

Carrier traps in 4H-SiC metal–oxide–semiconductor (MOS) capacitor and transistor devices were studied using the thermally stimulated current (TSC) method. TSC spectra from p-type MOS capacitors and n-channel MOS field-effect transistors (MOSFETs) indicated the presence of oxide traps with peak emission around 55 K. An additional peak near 80 K was observed due to acceptor activation and hole traps near the interface. The physical location of the traps in the devices was deduced using a localized electric field approach. The density of hole traps contributing to the 80-K peak was separated from the acceptor trap density using a gamma-ray irradiation method. As a result, hole trap density of N _t,hole = 2.08 × 10¹⁵ cm⁻³ at 2 MV/cm gate field and N _t,hole = 2.5 × 10¹⁶ cm⁻³ at 4.5 MV/cm gate field was extracted from the 80-K TSC spectra. Measurements of the source-body n ⁺–p junction suggested the presence of implantation damage in the space-charge region, as well as defect states near the n ⁺ SiC substrate.     

A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric

The programming characteristics of memories with different tunneling-layer structures (Si₃N₄, SiO₂ and Si₃N₄/SiO₂ stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO₂/Si₃N₄ stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO₂ or Si₃N₄ for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO₂/Si₃N₄ stacked tunneling layer at V_cg = 10 V and V_ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10¹⁶–2 × 10¹⁷ cm⁻³, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current.     

A green emitting iridium(III) complex with narrow emission band and its application to phosphorescence organic light-emitting diodes (OLEDs)

The homoleptic Ir(III) complex, fac-tris{2-(3′-trimethylsilylphenyl)-5-trimethylsilylpyridinato}iridium, has been synthesized and characterized to investigate the effect of the substitution of bulky silyl groups on the photophysical properties and electroluminescence (EL) characteristics of Ir(ppy)₃ (ppy = 2-phenylpyridine). The absorption, emission, cyclic voltammetry and electroluminescent performance of the complex have also been evaluated. A power efficiency of 17.3 lm/W at 10 mA/cm² compared to 11.7 lm/W for Ir(ppy)₃ is achieved with the new complex as a dopant in phosphorescent organic light-emitting diodes (OLEDs). In addition, the complex shows a narrow emission band of a small full width at half-maximum (fwhm, ca. 50 nm) value.     

Optimization of electric properties of high-k zirconium dioxide by varying deposition and annealing conditions

ZrO₂ thin films with a smooth surface were synthesized on silicon by atomic vapor deposition™ using Zr[OC(CH₃)₃]₄ as precursor. The maximum growth rate (7 nm min⁻¹) and strongest crystalline phase were obtained at 400 °C. The increase of the deposition temperature reduced the deposition rate to 0.5 nm min⁻¹ and changed the crystalline ZrO₂ phase from cubic/tetragonal to monoclinic. These films showed no enhancement of the dominating monoclinic phase by annealing. The values of the dielectric constant (up to 32) and leakage current density (down to 1.2×10⁻⁶ A cm⁻² at 1×10⁶ V cm⁻¹) varied depending on the deposition temperature and film thickness. The midgap density of interface states was N_it=5×10¹¹ eV⁻¹ cm⁻². The leakage current and the density of interface states were lowered by the annealing to 10⁻⁷ A cm⁻² at 1×10⁶ V cm⁻¹ and to 10¹⁰ eV⁻¹ cm⁻², respectively. However, this also led to a decrease of the dielectric constant.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.