The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

An analytical approach to dynamic crosstalk in coupled interconnects

This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation.     

A comprehensive submicrometer MOST delay model and its applicationto CMOS buffers

In this paper, an accurate delay model for MOS transistors in submicrometer CMOS digital circuits is presented. It takes into account a ramp shape input voltage and a feedforward capacitive coupling between gate and drain nodes, along with the main second-order effects present in short-channel MOS transistors. The proposed model shows an average agreement with SPICE simulations of 3% in the calculation of the propagation time, tested on a minimum inverter with a 0.7-μm CMOS reference technology for a wide range of input voltage slopes. An example of application in optimization algorithms regarding CMOS tapered buffers is also reported. A maximum error ranging from 3-6% with respect to SPICE has been found for the optimized circuits     

Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient IR voltage drops within a power distribution network. These transient IR voltage drops can affect the propagation delay of a CMOS logic gate, creating delay uncertainty within data paths. Analytical expressions characterizing these transient IR voltage drops are presented in this paper. The peak value of these transient IR voltage drops is within 6% as compared to SPICE. Circuit- and layout-level design constraints are also discussed to manage the peak value of the transient IR voltage drops. The propagation delay of a CMOS logic gate based on these analytical expressions is within 5% of SPICE while the estimate without considering transient IR voltage drops can exceed 20% for a 20 power line.     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

Wire shaping of RLC interconnects

The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tapering more attractive for RLC lines than for RC lines. For RLC lines, optimum wire tapering achieves a greater reduction in the signal propagation delay as compared to uniform wire sizing. For RLC lines, exponential tapering outperforms uniform repeater insertion. As technology advances, wire tapering becomes more effective than repeater insertion, since a greater reduction in the propagation delay is achieved. Optimum wire tapering achieves a reduction of 36% in the propagation delay in long RLC interconnect as compared to uniform repeater insertion.

Wire tapering can reduce both the propagation delay and power dissipation. Optimum tapering for minimum propagation delay reduces the propagation delay by 15% and power dissipation by 16% for an example circuit. The optimum tapering factor to minimize the transient power dissipation of a circuit is described in this paper. An analytic solution to determine the optimum tapering factor that exhibits an error of less than 2% is provided. Wire tapering is also shown to reduce the power dissipation of a circuit by up to 65%.

Wire tapering can also improve signal integrity by reducing the inductive noise of the interconnect lines. Wire tapering reduces the effect of impedance mismatch in digital circuits. The difference between the overshoots and undershoots in the signal waveform of an example clock distribution network is decreased by 34% as compared to a uniformly sized network producing the same signal characteristics.     

Pulsed wave interconnect

Pulsed wave interconnect is proposed for global interconnect applications. Signals are represented by localized wave-packets that propagate along the interconnect lines at the local speed of light to trigger the receivers. Energy consumption is reduced through charging up only part of the interconnect lines and using the voltage doubling property of the receiver gate capacitances. In a 0.18-/spl mu/m CMOS technology case study, SPICE simulations show that pulsed wave interconnect can save up to 50% of energy and /spl sim/30% of chip area in comparison with the repeater insertion method. A proposed signal splitting structure provides reasonable isolations between different receivers. Measured S-parameters of 3.8-mm interconnect lines fabricated through CMOS foundry showed that the distortion and attenuation of a pico second signal are much less serious than the theoretical predictions. Pulsed wave interconnect also enables time division application of a single line to boost its bit rate capacity. The use of nonlinear transmission lines (NLTL) is also proposed to overcome pulse broadening and attenuation caused by dispersion and frequency-dependent losses. Pulsed waves on an NLTL may be generated, transmitted, split and detected with components realizable in bulk and SOI CMOS technologies. Tapered NLTL can be used for pulse compression. NLTL edge sharpening abilities may be applicable for signal rise time control.     

Analytical transient response and propagation delay evaluation ofthe CMOS inverter for short-channel devices

In this paper an accurate, analytical model for the evaluation of the CMOS inverter transient response and propagation delay for short-channel devices is presented. An exhaustive analysis of the inverter operation is provided which results in accurate expressions of the output response to an input ramp. Most of the factors which influence the inverter operation are taken into account. The α-power law MOS model, which considers the carriers' velocity saturation effects of short-channel devices, is used. The final results are in excellent agreement with SPICE simulations     

Optimization of Driver Preemphasis for On-Chip Interconnects

In modern digital systems, on-chip interconnects have become the system bottleneck, limiting the performance of high-speed clock distributions and data communications in terms of speed and power dissipation. An inverse signaling analysis is developed to optimize the driving signal waveforms for lossy interconnects. By specifying the performance parameters, i.e., the signal swing and edge rate of the interconnect output signal, the corresponding input signals can be derived analytically. The result can be used to guide and optimize the design of interconnect preemphasis drivers. Numerical examples are shown for both lossy RC and RLC distributed lines. Analysis shows that optimized driving voltage and current can increase the interconnect bandwidth without voltage overshoot at the output. The significance of an interconnect inductance is also evaluated with this technique.     

Analysis and Modeling of Energy Consumption in RLC Tree Circuits

In this paper, the energy consumption of resistance-inductance-capacitance (RLC) trees is analytically modeled. In particular, the results obtained by the same authors for RC tree circuits are generalized, allowing for a deep understanding of the impact of the inductance. The modeling approach proposed relies on the adoption of an equivalent second-order RLC circuit, whose energy consumption is evaluated in a closed form. These results are then extended to RLC circuits with arbitrary order, deriving a simple and accurate model. The energy dependence on the input rise time is also analyzed in detail, identifying the ranges for which the RLC circuit can be approximated to a simple capacitance or an RC circuit. The model equations provide an insight into the dependence of the energy consumption on the circuit parameters. Indeed, the energy is explicitly expressed as a function of the resistances, capacitances and inductances of the original network. The energy model proposed is shown to be accurate enough for modeling purposes through comparison with SPICE simulations, as the error is typically in the order of a few percentage points.     

Estimating starting point of conduction of CMOS gates

To model effectively the output waveform and propagation delay of a CMOS gate, knowledge of the time point at which it starts to conduct is essential. An efficient method for calculating analytically this time point taking into account the structure of the gate and the input waveform, is introduced. Such a method can easily be integrated into a timing analysis system     

栅极触发PDSOI CMOS闩锁效应研究

测试了不同静态栅极触发电压(输入电压)下诱发CMOS闩锁效应需要的电源电压和输出电压(即将闩锁时的输出电压),发现静态栅极触发CMOS闩锁效应存在触发电流限制和维持电压限制两种闩锁触发限制模式,并且此栅极触发电压.输出电压曲线是动态栅极触发CMOS闩锁效应敏感区域与非敏感区域的分界线.通过改变输出端负载电容,测试出了不同电源电压下CMOS闩锁效应需要的栅极触发电压临界下降沿,并拟合出了0 pF负载电容时的临界下降沿,最终得出了PDSOI CMOS电路存在的CMOS闩锁效应很难通过电学方法测试出来的结论.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Comments on the optimum CMOS tapered buffer problem

Two recent papers, one by Li et al. (see ibid., vol 25, p1005-8,1990) and the other by Prunty and Gal (see ibid., vol. 27, no. 1, p118-9,1992), on the optimum CMOS tapered buffer problem are commented on. These papers claim that an equivalent “short-circuit” current capacitance should be added to the output capacitance of an inverter to account for the increased propagation delay obtained because of the short-circuit current that flows when a real input waveform is considered instead of an input step voltage. The reasoning results in an optimum tapering factor that is dependent on the waveform rise and fall times. However, the propagation delay only depends on the load capacitance and the ratio of the input to output transition times. In a fixed-taper buffer these transition times are equal making the optimum tapering factor independent of the “short-circuit” current. The comments also suggest an improved method of determining the optimum tapering factor in practical situations based on circuit simulations     

Design for velocity saturated, short-channel CMOS drivers withsimultaneous switching noise and switching time considerations

Design guidelines for velocity-saturated, short-channel CMOS drivers are presented in this paper based on approximating the package inductance by an effective, lumped, power-supply bus parasitic inductance. A worst-case maximum simultaneous switching noise V_GM and gate propagation delay time t_D,1/2 are treated as performance constraints for which driver design tradeoffs between driver geometry, the maximum number of simultaneously switched drivers, and the effective inductance are obtained. For typical loading conditions, design examples based on the proposed guidelines are shown by SPICE simulations using the MOS3 model to agree with both design goals within 10%     

Experimental confirmation of an accurate CMOS gate delay model forgate oxide and voltage scaling

MOSFET's and CMOS ring oscillators with gate oxide thicknesses from 2.58 nm to 5.7 nm and effective channel lengths down to 0.21 μm have been studied at voltages from 1.5 V to 3.3 V. Physical and electrical measurement of gate oxide thicknesses are compared. Ring oscillators' load capacitance is characterized through dynamic current measurement. An accurate model of CMOS gate delay is compared with measurement data. It shows that the dependence of gate propagation delay on gate oxide, channel length, and voltage scaling can be predicted     

1-V power supply high-speed digital circuit technology withmultithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-μm multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-μW/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-μm CMOS process