A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

High-performance solution-processed polymer space-charge-limited transistor

We demonstrate a polymer non-field-effect transistor in a vertical architecture with an Al grid embedded in a polymer sandwiched between another two electrodes. The Al grid containing high density of self-assembled submicron openings is fabricated by a non-lithography method. This device modulates the space-charge-limited current of a unipolar polymer diode with the Al grid. The operating voltage of the device is as low as 4 V, the on/off ratio is higher than one hundred, and the current gain is 10⁴. The current density is higher than 1 mA/cm².     

Recent progress of submicron CMOS using 6H-SiC for smart powerapplications

Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology; which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMBS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated     

Submicron T-shaped gate HEMT fabrication using deep-UV lithography

A new combination of low/high/low sensitivity tri-layer (PMMA/PMIPK/PMMA) resist system was used for deep UV lithography to-fabricate submicron T-shaped gate. Gate length as narrow as 0.2 μm is achieved. GaAs HEMTs with 0.3 μm T-shaped Ti/Pt/Au gate are fabricated using this technology. The HEMT demonstrated a 0.6 dB noise figure and 13 dB associated gain at 10 GHz. This deep UV lithography process provides a high throughput and low cost alternative to E-beam lithography for submicron T-gate fabrication     

A new FET-based integrated circuit technology: the SASSFET

The super self-aligned submicron single-metal FET (SASSFET), a FET-based integrated circuit technology suitable for fabrication of high-speed GaAs and InP circuits, is demonstrated. With nonalloyed source and drain contacts realized by MOCVD regrowth, the SASSFET is a uniform, dense, selfaligned, single-metal technology that achieves submicron dimensions with optical lithography. A 0.4 μm gate length junction HFET fabricated with the SASSFET technology has a transconductance of 380 mS/mm and a good high-frequency performance with f_τ of 45 GHz and f_max of 80 GHz     

Demonstration of submicron depletion-mode GaAs MOSFETs withnegligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga₂ O₃(Gd₂O₃) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f_T) of 17 GHz and a maximum oscillation frequency (f_max) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs     

Radiation effects of e-beam fabricated submicron NMOS transistors

This paper reports radiation effects of submicron NMOS devices fabricated by e-beam lithography. This study was initiated because e-beam lithography creates neutral traps in the gate oxides of MOS devices, which may make these devices more sensitive to radiation. Indeed, we have found that for radiation doses above 10 Krad, the threshold shift for an e-beam fabricated device is twice that for the corresponding device made by optical lithography. However, with the submicron process used here the threshold shift for both types of device is quite low (<100mV below 10 Krad), Moreover, there was no correlation observed between radiation sensitivity and device gate length.     

Operability analysis of submicron CMOS-based VLSI RAMs operated under extreme thermal conditions

Variations in the characteristics of the memory cells of submicron CMOS RAMs caused by changes in temperature were simulated and experimentally investigated in a wide temperature range of minus 50°C to +150°C. It was found that submicron VLSI circuits fabricated on the basis of the 0.35-μm bulk-CMOS technology with epitaxial layers and of the industrial 0.18-μm bulk-CMOS technology are, in the large, characterized by high maximum permissible temperatures. The simulation results were confirmed by the tests of submicron 0.35- and 0.18-μm CMOS RAMs based, respectively, on 6-transistor and 12-transistor memory cells with heavy-ion tolerant (HIT) and dual interlocked storage-cell (DICE) structures. The results of the investigation allow one to make a reasoned selection of memory cells to be used in practical embodiments of VLSI static RAMs intended to operate under extreme conditions     

High-speed low-power circuits fabricated using a submicron NMOS technology

We present results on very high-speed low-power devices and circuits fabricated using a NMOS technology scaled to submicron dimensions. These results illustrate the electrical behavior of single minimum-size devices, and present the performance of several submicron circuits, such as ring oscillators, a 3-GHz divide-by-two counter and a 90- MHz 16 × 16 multiplier.     

A novel fabrication of polymer film with tapered sub-wavelength structures for anti-reflection

This paper presents a cost-effective method to fabricate tapered sub-wavelength structures (SWSs) on the polycarbonate (PC) film using gas-assisted hot embossing with anodic aluminum oxide (AAO) template. The AAO template with array of high-aspect-ratio submicron holes was fabricated using a two-step anodization process. The soften polymer is then pressurized by gas to fill deep into the nano-holes, tapered SWSs could be generated by directly separating the PC film from AAO template during the de-molding process. The heights were up to about 260 nm. The fabricated PC film reduces the reflectivity from 8.9% in a bare film to 2% with tapered SWSs at the wavelength of 550 nm. The AAO template can be used repeatedly.     

A pixellated grating array using photoelectrochemical etching on aGaAs waveguide

We have demonstrated and evaluated a grating array outcoupler fabricated by photoelectrochemical (PEC) etching, a manufacturable and practical approach for fabrication of grating-based III-V semiconductor waveguide devices. An array of submicron period gratings was etched into photolithographically delineated areas in a single PEC step. The fabricated devices are: 10-μm wide rib waveguides with 0.35-μm first-order outcoupling gratings; and 10-μm wide rib waveguides with 10 μm×10 μm pixellated areas of gratings. Device characterization demonstrates the effectiveness of outcoupling grating fabrication using PEC and that the pixellated grating outcoupler is an effective and simple means of generating an optical beam array     

Design and modeling of self-aligned nano-imprinted sub-micrometer pentacene-based organic thin-film transistors

Sub-micrometer channel length (0.5 μm) organic thin-film transistors (OTFTs) are demonstrated using a process flow combining nano-imprint lithography (NIL) and self-alignment (SA). A dedicated test structure was designed and samples were fabricated on 4-in. plastic foils using a p-type sublimated small molecule (pentacene) as semiconductor. Field-effect mobilities, in saturation, between 0.1 and 1 cm²/Vs were obtained not only for the supermicron OTFTs but also for the submicron OTFTs. Those devices were used to select a model based on the “TFT Generic Charge Drift model” which works well for a broad range of channel lengths including the submicron OTFTs. We show that these OTFTs can be accurately modeled, thus giving access to complex circuit simulations and design.     

Residue-free room temperature UV-nanoimprinting of submicron organic thin film transistors

In this study we report on an innovative nanoimprint process for the fabrication of entirely patterned submicron OTFTs in a bottom-gate configuration. The method is based on UV-Nanoimprint Lithography (UV-NIL) combined with a novel imprint resist whose outstanding chemical and physical properties are responsible for the excellent results in structure transfer. In combination with a pretreated stamp the UV-curable resist enables residue-free imprinting thus making etching obsolete. A subsequent lift-off can be done with water. The UV-NIL process implies no extra temperature budget, is time saving due to short curing times, eco-friendly due to a water-based lift-off, simple because it is etch-free and completely r2r compatible. It works perfectly even if ultra-thin organic and hybrid films are used as gate dielectrics. On this basis entirely patterned functional submicron OTFTs with pentacene as the semiconductor are fabricated showing clear saturation, low switch-on voltage (～3 V) and a sufficiently high on–off ratio (10³).     

Self-aligned submicron gate digital GaAs integrated circuits

Digital normally-off (ENFET) GaAs integrated circuits have been fabricated using a novel self-aligned gate process that has produced high speed ring-oscillators with propagation delays as low as 25 ps and other low power circuits with power dissipation as small as 16 µW (at room temperature). The process is unique in that it permits control of parasitic FET source resistance and gate capacitance and also can achieve submicron gate lengths using conventional optical lithography.     

Transferred substrate Schottky-collector heterojunction bipolartransistors: first results and scaling laws for highfmax

Unlike normal heterojunction bipolar transistors (HBT's), transferred substrate Schottky-collector HBT's (SCHBT's) exhibit substantial increases in f_max as the emitter and collector stripes are scaled to deep submicron dimensions. First generation InAlAs/InGaAs SCHBT's with aligned 1-μm emitter and collector stripes have been fabricated     

Scaling I2L for VLSI

Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I²L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I²L devices with geometries >1 µm is described and examples of scaled devices fabricated with e-beam slice writing techniques are given. It is shown that the I²L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submicron geometries are summarized and the performance attainable with a submicron device design is predicted.     

A novel method to characterize parasitic capacitances in MOSFET's

A new technique exploiting the body effect is presented to separate intrinsic from extrinsic capacitances in submicron MOSFET's. The method has been validated using 2D numerical simulations and results obtained with transistors fabricated with 0.7 μm CMOS technology are presented     

Impulse responses of submicron GaAs photodetectors

Metal–semiconductor–metal photodetectors with different submicron spacings (d = 100, 300, 500, 700 and 900 nm) were fabricated on GaAs with a carrier recombination time of 100 ps by electron beam lithography. Temporal responses of the detectors were measured by photoconductive sampling in order to identify factors which limits the response speeds. At a low excitation of <100 μW, the response speeds of 100, 300 and 500 nm spacing detectors are limited by parasitic capacitances of the submicron structures. The speeds of 700 and 900 nm spacing detectors are limited by an electron/hole transport in the semiconductor. At a high excitation of >100 μW, the response speeds of the all spacing detectors are limited by field screening caused by electron–hole plasma.     

Neutron-induced B fission as a major source of soft errors in high density SRAMs

The impact of cosmic neutron induced ¹⁰B fission in production submicron SRAM devices is reported for the first time. Using a cold neutron beam to accelerate soft error rate events, we unambiguously demonstrate that neutron induced ¹⁰B fission can be a significant source of soft errors in deep-submicron SRAMs fabricated with borophosphosilicate glass.     

Scaling I/SUP 2/L for VLSI

Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I/SUP 2/L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I/SUP 2/L devices with geometries >1 /spl mu/m is described and examples of scaled devices fabricated with e-beam slice writing techniques are given. It is shown that the I/SUP 2/L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submicron geometries are summarized and the performance attainable with a submicron device design is predicted.