TORUS-switch: a scalable internal speed-up ATM switch architectureand its 5 Gbit/s switch LSI

A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient     

56 byte optical cell selection at 55 Gbit/s in bit-interleavemultiplexing photonic ATM switch

Experiments on selecting 56 byte optical cells out of a four-channel bit-interleave multiplexed 55 Gbit/s pulse stream are carried out using a nonlinear optical loop mirror (NOLM) including a chalcogenide glass fibre     

Scalable 10 Gbit/s 4×20.25 μm CMOS/SIMOX ATM switch LSIcircuit based on distributed contention control

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput, 0.2 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption     

A 100-Gb/s throughput ATM switch MCM with a 320-channel paralleloptical I/O interface

For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-μm complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface     

80 Gbit/s pulsewidth-maintained wavelength conversion based on HNLDSF-NOLM including transmission over 80 km of conventional SMF

80 Gbit/s pulsewidth-maintained wavelength conversion based on a high-nonlinearity dispersion shifted fibre nonlinear optical loop mirror (DSF-NOLM) is realised and penalty-free transmission over 80 km conventional single mode fibre and 12 km dispersion compensating fibre of the converted signal is demonstrated for the first time     

43 Gbit/s automatic gain control amplifier based on InP SHBT technology

A high bandwidth automatic-gain-control (AGC) amplifier has been designed and characterised. Fabricated in InP single-heterojunction-bipolar transistor (SHBT) technology, the measured bandwidth of the amplifier is 36 GHz with maximum small signal gain 22 dB. Capable of operating at 43 Gbit/s, this is believed to be the fastest AGC amplifier reported to date.     

基于DSP实现的100 Gbit/s DP-QPSK系统相干接收技术

对100 Gbit/s 偏振复用-正交相移键控（DP-QPSK）系统中使用数字信号处理（DSP）技术同时实现对光信号色散补偿、偏振解复用和相位估计的方案进行了讨论,并采用OptiSystem 9.0软件对该方案的效果进行了验证,仿真结果表明该技术方案实现简单且可靠性高,对优化相干光检测硬件有参考意义。     

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 μm technology and the ICM, a 0.7 μm CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper     

Cell processing LSIs for 2.4 Gbit/s SDH-based ATM transmission system

Introduces cell processing large-scale integrated circuits (LSIs) suitable for byte-oriented systems operating at 2.4 Gbit/s. The LSIs are based on a newly proposed cell delineation circuit which uses a pipeline processing technology to realise byte-by-byte shift operations, an error-detect and error-correct circuit and a descrambling circuit. Prototype LSIs, constructed with a super-selfaligned process technology (SST), are tested at up to 3.7 Gbit/s.<>     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

80 Gbit/s simultaneous photonic demultiplexing based on OTDM-to-WDMconversion by four-wave mixing with supercontinuum light source

A novel method for all-optical all-channel simultaneous demultiplexing based on OTDM-to-WDM conversion by four-wave mixing with a highly chirped rectangular shaped supercontinuum source is proposed. Error-free 80 to 10 Gbit/s demultiplexing operation in eight channels is experimentally demonstrated     

40 Gbit/s limiting output buffer in 80 nm CMOS

A 40 Gbit/s 1V limiting output buffer for an AC-coupled 50 /spl Omega/ load with a differential output swing of 660 mV and a gain of 18 dB is presented. A power consumption of only 24 mW and a simulated risetime of 11 ps are achieved by means of a systematic buffer optimisation.     

超100 Gbit/s高速正交频分复用传输技术

光纤通信网络已进入速率超100 Gbit/s时代,并向400 Gbit/s/1 Tbit/s迅速发展。目前在400 Gbit/s/1 Tbit/s 速率以上的多数试验中,高速 O-OFDM(光正交频分复用)可行的传输方案有 CO-OFDM(相干探测光 OFDM)、AO-OFDM(全光OFDM)和混合型电光 OFDM三种系统。文章对比分析了三种高速 O-OFDM系统发射端和接收端结构,综述了三种系统在高速光纤传输中的性能优缺点以及下一步研究的重点。     

An ultrafast photonic ATM switch based on bit-interleavemultiplexing

An optical ATM switch is proposed in which cells from individual input channels are time-division multiplexed in a bit-interleave manner. This switch can easily handle multicast switching because it is based on a broadcast-and-select network. Compared to an alternative switch that uses a cell-interleave time-division multiplexing scheme, the proposed optical switch has a much simpler structure. It does not need a cell compressor at each input and a cell expander at each output, which greatly reduces hardware complexity. Feasibility analyzes showed that a 64×64 photonic ATM switch with 2.5 Gb/s input/output is possible using the proposed technology. In an experimental demonstration, 4 b cells were selected from a 55 Gb/s bit-interleave multiplexed cell stream by using a new nonlinear optical fiber switch. With its high switch throughput, our switch is a strong candidate for future large-capacity optical switching nodes     

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both$f_T$and$f_max $. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600$hboxmV_ pp$. The extracted 40 GHz clock signal shows a phase noise as low as$- hbox98~dBc/hboxHz$at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of$-hbox4.8~V$, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.     

Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To improve I/O pin number limits, the single-ended ECL circuit operates with a reference signal directly generated from the input signal itself. The reference level can change dynamically to achieve a larger noise margin for the input signal. Experimental results show that operation up to 3.4 Gbit/s with a large level margin can be attained     

40 Gbit/s pulsewidth-maintained wavelength conversion based on ahigh-nonlinearity DSF-NOLM

The authors present results showing that walkoff and dispersion effects are reduced when only 1 km HNL-DSF fibre is used in a nonlinear optical loop mirror (NOLM). Broadband and pulsewidth-maintained wavelength conversion at 40 Gbit/s based on a high-nonlinearity DSF-NOLM is obtained     

40 Gbit/s/ch 2/spl times/2 switch IC using InP HEMTs

A low-power 2/spl times/2 switch IC using InP HEMTs as cold FETs is presented. It has a logic-level-independent interface since no signal line is grounded. The IC yields low insertion loss of 1.5-2.7 dB and high isolation of >21.2 dB below 30 GHz. When two 40 Gbit/s signals were input, error-free operation was confirmed with virtually zero power dissipation.     

Dispersion compensated 80 Gbit/s WDM transmission over 1171 kmstandard singlemode fibre

WDM transmission experiment at 80 Gbit/s (8×10 Gbit/s, 0.8 nm channel spacing) over 1171 km of standard singlemode fibre has been performed with a 90.1 km recirculating loop incorporating a dispersion compensation fibre and gain-equalising optical bandpass filters     

80 Gbit/s wavelength conversion using MQW electroabsorption modulator in delayed-interferometric configuration

Absorption recovery time and cross-phase modulation characteristics of an MQW electroabsorption modulator (EAM) were experimentally analysed. 80 Gbit/s error-free operation of a wavelength converter using the MQW EAM in a delayed-interferometer configuration was demonstrated for the first time.