A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation

This work presents the design of a new and unique design technique of constant loop bandwidth and phase-noise cancellation in a wideband ΔΣ fractional-N PLL frequency synthesizer. Phase noise performance of the proposed ΔΣ fractional-N PLL frequency synthesizer has been verified using CppSim simulator with the help of transistor level simulation results in Cadence SpecctreRF. Transient response of the proposed ΔΣ fractional-N PLL has been verified in transistor level simulation using Cadence SpectreRF in 0.13 μm standard CMOS process. The proposed phase-noise cancellation and constant loop bandwidth in wideband ΔΣ fractional-N PLL reduces the out of band phase noise by 18 dBc/Hz at 2 MHz offset frequency for a closed loop bandwidth of 1 MHz, when I_CP,max is equal to 2.6 mA. PLL locking time has been reduced with phase-noise cancellation and a constant loop bandwidth calibration circuits using the proposed CP unit current cell for the mismatch compensated PFD/DAC in wideband ΔΣ fractional-N PLL frequency synthesizer. Optimum phase noise performance can be achieved with the help of proposed design technique. Proposed ΔΣ fractional-N PLL frequency synthesizer is locked within 14.0 μs with an automatic frequency control circuit of the LC VCO and a constant loop bandwidth calibration circuit through the use of proposed CP unit current cell for the mismatch compensated PFD/DAC for the phase-noise cancellation in worst case condition of K_VFC = 10 and K_LBC = 150. Our new design technique can be extensively integrated for wideband fractional-N PLL for new type of wireless communication paradigm using the thinnest channel subharmonic transistor and low power devices, and it has the potential to open a new era of fractional-N PLLs for wideband application.     

一个自调谐,自适应的1.9GHz分数/整数频率综合器

本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断 ΣΔ 调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz~2.1GHz的调谐范围.该频率综合器采用0.18 μ m,1.8V SMIC CMOS工艺实现.SpectreVerilog仿真表明:该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15 μ s的锁定时间.     

一种应用于GNSS接收机常数环路带宽的小数频率合成器

提出了一种应用于手持式民用GNSS接收机常数环路带宽的小数频率合成器,并在0.13μm 1P6M 的CMOS工艺中实现。通过离散的工作区域,LC-VCO用简单的结构获得宽的调节范围和小的压控灵敏度。提出的杂散抑制技术来最小化由于鉴频鉴相器和电荷泵引入的相位偏移。当PLL输出频率改变或温度变化时,通过自动环路校正模块自适应调整电荷泵电流保持优化的环路带宽不变。测试结果显示,该频率合成器带内相位噪声小于-93dBc（10 kHz 频率偏移处）,杂散小于-70 dBc, 环路带宽变化小于?3%;在1V的电源供电下,整个合成器（不包括本振测试buffer）消耗4.5mA电流,面积为0.5mm2。     

U波段小数分频锁相环型频率综合器

使用0.18μm1.8VCMOS工艺实现了U波段小数分频锁相环型频率综合器,除压控振荡器(VCO)的调谐电感和锁相环路的无源滤波器外,其他模块都集成在片内。锁相环采用了带有开关电容阵列(SCA)的LC-VCO实现了宽频范围,使用3阶MASHΔ-Σ调制技术进行噪声整形降低了带内噪声。测试结果表明,频率综合器频率范围达到650～920MHz;波段内偏离中心频率100kHz处的相位噪声为-82dBc/Hz,1MHz处的相位噪声为-121dBc/Hz;最小频率分辨率为15Hz;在1.8V工作电压下,功耗为22mW。     

A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation

A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip loop filter. In addition to the adaptive calibration technique, the IC incorporates a dynamic charge pump biasing technique to reduce power dissipation. The worst-case phase noise of the IC is -101 dBc/Hz and -124 dBc/Hz at 100 kHz and 3 MHz offsets, respectively, and the adaptive phase noise cancellation technique has a worst-case settling time of 35 mus . The IC is implemented in 0.18 CMOS technology. It measures 2.2 x 22 mm² and its core circuitry consumes 20.9 mA from a 1.8 V supply.     

A 1.8-GHz self-calibrated phase-locked loop with precise I/Qmatching

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-μm CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply     

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-$mu$m CMOS

A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine frequency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35-mum CMOS technology. At 2.5GHz it achieves 1.8-MHz bandwidth, while the settling time within 30ppm for an 80-MHz step is 3 mus. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is 48dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.     

A Quantization Noise Pushing Technique for $DeltaSigma$ Fractional- $N$ Frequency Synthesizers

This paper demonstrates our proposed quantization noise pushing technique, which moves the quantization noise to higher frequencies and utilizes the low-pass characteristic of the phased-lock loop (PLL) to further suppress the quantization noise. In addition, it can separate the operating frequency of the DeltaSigma modulator and the comparison frequency of the phase/frequency detector (PFD) so as to reduce the loop gain of the PLL and lower the in-band phase noise. This synthesizer was fabricated using the UMC 0.18-mum CMOS process. The chip area measures 0.85 mm². The supply voltage is 2 V, corresponding to a total power consumption of 26.8 mW. The experimental results show that, with this technique, the in-band phase noise can be lowered by 12 dB, while the out-of-band phase noise can be reduced by more than 15 dB, compared to a synthesizer with the same PFD comparison frequency.     

A CMOS monolithic ΔΣ-controlled fractional-N frequencysynthesizer for DCS-1800

A monolithic 1.8-GHz ΔΣ-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-μm CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2×2 mm². To investigate the influence of the ΔΣ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in ΔΣ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints     

A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-/spl mu/m CMOS

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-/spl mu/m CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.     

A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation

A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.     

A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.     

Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

正A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed.The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer.An auxiliary non-volatile memory(NVM) is embedded to avoid the repetitive calibration process and to save power in practical application.This PLL is implemented in a 0.18μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5μs over the entire frequency range.The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz.The measured phase noise of frequency synthesizer is about-115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc.The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.     

A 0.13μm CMOS △∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers.A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor.The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) △ ∑ modulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.     

A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.     

A CMOS frequency synthesizer with an injection-locked frequencydivider for a 5-GHz wireless LAN receiver

A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 μm CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc     

A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13-$mu{rm m}$ CMOS

In this letter, a fractional-N frequency synthesizer based on an offset phase-locked loop (OPLL) architecture is presented. The proposed synthesizer achieves low-noise as the two low-pass filters that are inherent in the OPLL highly suppresses the quantization noise from the delta-sigma modulator. In addition, it consumes low power by employing charge-recycling technique in the sub-PLL. A prototype synthesizer implemented in 0.13 $mu{rm m}$ CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of power.      

A low-spurious fast-hopping MB-OFDM UWB synthesizer

A frequency synthesizer for the ultra-wide band(UWB)group # 1 is proposed.The synthesizer uses a phase locked loop(PLL)and single-sideband(SSB)mixers to generate the three center frequencies of the first band group by mixing 4224 MHz with ±264 MHz and 792 MHz,respectively.A novel multi-QSSB mixer is designed to combine the function of frequency selection and frequency conversion for low power and high linearity.The synthesizer is fabricated in Jazz 0.18-μm RF CMOS technology.The measured reference spur is as low as-69 dBc and the maximum spur is the LO leakage of-32 dBc.A low phase noise of-110 dBc/Hz @ 1 MHz offset and an integrated phase noise of 1.86°are achieved.The hopping time between different bands is less than 1.8 ns.The synthesizer consumes 30 mA from a1.8 V supply.     

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

正A constant loop bandwidth fractional-TV frequency synthesizer for portable civilian global navigation satellite system(GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced.Via discrete working regions,the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain.Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps.The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies.Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc;the bandwidth varies by±3%for all the GNSS signals.The whole synthesizer consumes 4.5 mA current from a 1 V supply,and its area(without the LO tested buffer) is 0.5 mm~2.     

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz.