Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

We investigate the reliability of pFET-based EEPROMs with 70-/spl Aring/ tunneling oxides fabricated in standard foundry 0.35-/spl mu/m, 0.25-/spl mu/m, and 0.18-/spl mu/m logic CMOS processes. The floating-gate memory cell uses Fowler-Nordheim tunneling erase and impact-ionization generated hot-electron injection for programming. We show that charge leakage is dominated by the leakage through interlayer dielectrics. We propose a retention model and show the data retention lifetime exceeds 10 years. These results demonstrate the feasibility of producing nonvolatile memory using standard logic processes that have a 70-/spl Aring/ oxide.     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

Analysis of tunneling currents in multilayer black phosphorous and $$\hbox {MoS}_{2}$$ non-volatile flash memory cells

This paper presents a theoretical study of tunneling current density and the leakage current through multi-layer (stacked) trapping layer in the gate dielectric in MOS non-volatile memory devices. Two different 2D materials (\(\hbox {MoS}_{2}\) and black phosphorous) with a combination of high-k dielectric (\(\hbox {HfO}_{2}\)) have been used for the study with differently ordered stacks i.e., as trapping layer and substrate. The material properties of 2D materials like density of states, effective mass and band structure has been evaluated using density functional theory simulations. Using the Maxwell–Garnett effective medium theory we have calculated the effective barrier height, effective bandgap, effective dielectric constant and effective mass of the gate dielectric stacks. By applying WKB approximation in the multi-layer trapping layer we have studied the effect of the direct and Fowler–Nordheim tunneling currents. The leakage current in all the different stack combinations used has also been evaluated. The results obtained have shown to match the required dynamics of a memory device.     

Physics-based modeling approaches of resistive switching devices for memory and in-memory computing applications

The semiconductor industry is currently challenged by the emergence of Internet of Things, Big data, and deep-learning techniques to enable object recognition and inference in portable computers. These revolutions demand new technologies for memory and computation going beyond the standard CMOS-based platform. In this scenario, resistive switching memory (RRAM) is extremely promising in the frame of storage technology, memory devices, and in-memory computing circuits, such as memristive logic or neuromorphic machines. To serve as enabling technology for these new fields, however, there is still a lack of industrial tools to predict the device behavior under certain operation schemes and to allow for optimization of the device properties based on materials and stack engineering. This work provides an overview of modeling approaches for RRAM simulation, at the level of technology computer aided design and high-level compact models for circuit simulations. Finite element method modeling, kinetic Monte Carlo models, and physics-based analytical models will be reviewed. The adaptation of modeling schemes to various RRAM concepts, such as filamentary switching and interface switching, will be discussed. Finally, application cases of compact modeling to simulate simple RRAM circuits for computing will be shown.     

The Modeling and Calculation of One Transistor Memory Devices

Metal/Ferroelectrics/Metal/Insulator/Si (MFMIS) and Metal/Ferroelectrics/ Insulator/Si (MFIS) one-transistor devices are being proposed for non-volatile memory applications. In order to determine the basic theory of one-transistor memory devices, we use equivalent circuits to model and calculate the basic properties of one-transistor memory devices. The capacitance of MFMIS and MFIS capacitors, memory windows, operation voltages, threshold voltages, and both switching and retention properties of one-transistor memory devices have also been calculated. According to the modeling and calculation, the ferroelectric materials with lower dielectric constant (?), low polarization (P_R), appropriate coercive field and square hysteresis loop are required for one-transistor memory devices and low voltage applications. High dielectric constant insulator materials may improve the performance of one-transistor memory devices. In addition, the effects of depolarization fields, leakage current, and defect density on the switching and retention properties of one-transistor memory devices are also calculated. Based on the modeling and calculation, the retention problem dealing with depolarization fields and leakage current is a big challenge for one-transistor memory devices.     

VSP—a quantum-electronic simulation framework

The Vienna Schrödinger-Poisson (VSP) simulation framework for quantum-electronic engineering applications is presented. It is an extensive software tool that includes models for band structure calculation, self-consistent carrier concentrations including strain, mobility, and transport in transistors and heterostructure devices. The basic physical models are described. Through flexible combination of basic models sophisticated simulation setups for particular problems are feasible. The numerical tools, methods and libraries are presented. A layered software design allows VSP’s existing components such as models and solvers to be combined in a multitude of ways, and new components to be added easily. The design principles of the software are explained. Software abstraction is divided into the data, modeling and algebraic level resulting in a flexible physical modeling tool. The simulator’s capabilities are demonstrated with real-world simulation examples of tri-gate and nanoscale planar transistors, quantum dots, resonant tunneling diodes, and quantum cascade detectors.     

继电保护装置存储异常变位的容错设计与应用

继电保护装置用到的存储器类型包括非易失性存储器和随机存取存储器2种。这2种存储器的异常变位(单粒子效应)将导致继电保护装置的关键数据丢失、程序运行异常、整机功能失效和误动。文中针对随机存取存储器异常变位,设计了实时内存变位监控及变位恢复机制,避免了异常变位造成继电保护装置功能失效的问题;针对非易失性存储器异常变位,设计了冗余加固的文件存储方法,消除了异常变位对继电保护装置的影响。文中所提设计方法通过中子散列试验得到了实际验证,已应用于超高压继电保护装置并挂网运行,方案切实有效。     

Ferroelectric polymer Langmuir-Blodgett films for nonvolatile memory applications

We review the potential for integrating ferroelectric polymer Langmuir-Blodgett (LB) films with semiconductor technology to produce nonvolatile ferroelectric random-access memory (NV-FRAM or NV-FeRAM) and data-storage devices. The prototype material is a copolymer consisting of 70% vinylidene fluoride (VDF) and 30% trifluoroethylene (TrFE), or P(VDF-TrFE 70:30). Recent work with LB films and more conventional solvent-formed films shows that the VDF copolymers are promising materials for nonvolatile memory applications. The prototype device is the metal-ferroelectric-insulator-semiconductor (MFIS) capacitance memory. Field-effect transistor (FET)-based devices are also discussed. The LB films afford devices with low-voltage operation, but there are two important technical hurdles that must be surmounted. First, an appropriate method must be found to control switching dynamics in the LB copolymer films. Second, the LB technology must be scaled up and incorporated into the semiconductor-manufacturing process, but since there is no precedent for mass production of LB films, it is difficult to project how long this will take.     

Combined Nanoscale and Device-Level Degradation Analysis of $hbox{SiO}_{2}$ Layers of MOS Nonvolatile Memory Devices

In this paper, the impact of an electrical stress applied on MOS structures with a 9.8-nm-thick $hbox{SiO}_{2}$ layer has been investigated at the device level and at the nanoscale with conductive atomic force microscopy (AFM). The goal is to correlate both kinds of measurements when studying the degradation and breakdown (BD) of tunnel oxides of nonvolatile memory devices. In particular, the generation of defects and its impact on leakage current and charge trapping in the tunnel oxide have been analyzed through spectroscopic measurements and current images. The properties and energy of the stress-induced defects (before and after BD) have been roughly estimated by thermally stimulated luminescence and AFM measurements.      

Evaluation of SiO/sub 2/ antifuse in a 3D-OTP memory

We have evaluated an antifuse technology used in a novel three-dimensional one-time-programmable (3D-OTP) nonvolatile solid-state memory. The 3D-OTP memory uses deposited polysilicon antifuse sandwiches to build its memory cells. The polysilicon based SiO/sub 2/ antifuse show different breakdown characteristics compared to conventional traditional gate oxides. Long-term storage tests show that this 3D-OTP solid-state memory not only can be a general purpose ROM, but also can be an ideal media for archiving.     

Simulation of thin-TFETs using transition metal dichalcogenides: effect of material parameters,gate dielectric on electrostatic device performance

In recent years, significant of scientific research effort has focused on the investigation of transition metal dichalcogenides (TMDC) and other two-dimensional (2D) materials like graphene or boron nitride. Theoretical investigation on the physical aspects of these materials has revealed a whole new range of exciting applications due to wide tunability in electronic and optoelectronic properties. Besides theoretical exploration, these materials have been successfully implemented in electronic and optoelectronic devices with promising results. In this work, we have investigated the effect of monolayer TMDC materials and monolayer TMDC alloys on the performance of thin tunneling field-effect transistors or thin-TFETs. These are promising electronic devices that can achieve steep switching characteristics. We have used the self-consistent determination of the conduction and valence band levels in the device and a simplified model of interlayer tunneling current reported in recent literature that treats scattering semiclassically and incorporates the energy broadening effect using a Gaussian approximation . We have also explored the effect of gate dielectric material variation, interlayer dielectric variation, top gate metal workfunction on the performance of the device. Our study shows that proper choice of material in the top and bottom layers, optimization of materials used as gate and interlayer dielectric are necessary to extract the full potential of these devices. The electron affinity and bandgap of the TMDCs used in different layers effectively control the threshold voltage and current in the device. As seen from our simulation, interlayer materials with high dielectric constant can degrade subthreshold device performance, increase threshold voltage, whereas lowering interlayer thickness could increase device ‘on’ current at the expense of degraded subthreshold performance.     

Multiscale modeling of oxide RRAM devices for memory applications: from material properties to device performance

RRAM devices have been subjected to intense research efforts and are proposed for nonvolatile memory and neuromorphic applications. In this paper we describe a multiscale modeling platform connecting the microscopic properties of the resistive switching material to the electrical characteristics and operation of RRAM devices. The platform allows self-consistently modeling the charge and ion transport and the material structural modifications occurring during RRAM operations and reliability, i.e., conductive filament creation and partial disruption. It allows describing the electrical behavior (current, forming, switching, cycling, reliability tests) of RRAM devices in static and transient conditions and their dependence on external conditions (e.g., temperature). Thanks to the kinetic Monte Carlo approach, the inherent variability of physical processes is properly accounted for. Simulation results can be used both to investigate material properties (including atomic defect distributions) and to optimize stack and bias pulses for optimum device performances and reliability.     

Efficient calculation of lifetime based direct tunneling through stacked dielectrics

We present the efficient simulation of lifetime based tunneling in CMOS devices through layers of high-κ dielectrics which relies on the precise determination of quasi-bound states (QBS). The QBS are calculated using the perfectly matched layer (PML) method. Introducing a complex coordinate stretching allows artifical absorbing layers to be applied at the boundaries. The QBS appear as the eigenvalues of a linear, non-Hermitian Hamiltonian where the QBS lifetimes are directly related to the imaginary part of the eigenvalues. The PML method turns out to be an elegant, numerically stable, and efficient method to calculate QBS lifetimes for the investigation of direct tunneling through stacked gate dielectrics.     

Dielectric strength of series connected vacuum gaps

A simple procedure to obtain an analytical equation for the distribution function of breakdown voltage in devices containing an arbitrary number of identical elements in series is proposed. The obtained results make possible to analyze an influence of static properties of the elements and their number on the dielectric strength of a device as a whole. The probability of the breakdown of the switching device is calculated using the empirical distribution functions of breakdown voltages of each TVS. The Weibull plots are used to analyze the breakdown test results. The measurement of the dielectric strength performed for AC and DC devices shows a good agreement with the calculated data.     

Nanomagnetic logic: compact modeling of field-coupled computing devices for system investigations

In this paper we investigate error rates of nanomagnetic logic devices with perpendicular magnetization by compact modeling. Two different types of nanomagnets for information propagation and logic computing are introduced. The switching behavior of field-coupled nanomagnets is measured and analyzed. A compact model is derived from physics and experimental results are applied to the magnetic compact model. General requirements for fabrication parameters and clocking fields for reliable operation are extracted. We perform simulations and measurements on single devices to demonstrate the accuracy of the macromodel. Simulations on complex systems show that the error rate of a field-coupled magnetic system strongly depends on the variation of the switching field and the strength of the coupling field between the nanomagnets. The error rate of a 1-bit full adder is investigated for varying dot parameters. The results demonstrate the importance of fast simulation tools for investigations on the design of nanomagnetic computing devices and systems.     

Designing digital circuits using 3D nanomagnetic logic architectures

The approach to designing digital circuits using three-dimensional (3D) perpendicular nanomagnetic logic (pNML) is thoroughly investigated. Nanomagnetic logic (NML) technology eventually optimizes the circuit performance in comparison with conventional metal–oxide–semiconductor (MOS) technology, which suffers from the hot carrier, velocity saturation, and short-channel effects, which may considerably degrade device performance. In contrast, nanomagnetic logic is immune to radiation; it behaves as nonvolatile memory and shows zero leakage current, as required for use in high-speed and low-cost nanoelectronics applications. In this paper, novel and organized designs, e.g., for 3D Ex-OR, parity generator, parity checker, multiplexer, and arithmetic logic unit (ALU) functionality, are synthesized using pNML technology. Previous designs are not compact in terms of delay, layer count, or bounded area. To overcome this, new designs for the mentioned functionalities are proposed based on pNML with smaller area and lower latency compared with previous circuits.

     

LASAR仿真中的VITAL建模方法研究

应用LASAR仿真方法时,只有具备了电路板网络表和电路板上所有数字逻辑器件的模型,才能够生成有效的电路板测试数据.构建完整的器件库,是有待研究的1项重要内容.VITAL建模是众多建模方法中较科学并容易实现的途径,它为ASIC库的建立、电路设计的描述提供了便利的、格式相对固定的描述方法.本文介绍VITAL的基本内容,并对...     

A simulation framework for modeling charge transport and degradation in high-k stacks

In this paper we present a comprehensive physical model that describes charge transport and degradation phenomena in high-k stacks. The physical mechanisms are modeled using a novel material-related approach that includes in a self-consistent fashion the charge transport (dominated by defect-assisted contribution), power dissipation and temperature increase, defect generation, and ion and vacancy diffusion and recombination. The physical properties of defects, which play a crucial role in determining the electrical behavior of the high-k stacks, depend on their atomistic configurations, as calculated using ab-initio methods. This simulation framework represents a powerful tool to interpret electrical characterization measurements. In addition, it can be used to optimize logic and memory device stacks thanks to its predictive statistical capabilities that allow reproducing gate current, threshold voltage increase and time to breakdown (TDDB) statistics. Simulation results performed using this simulation package are shown to reproduce accurately leakage current, Stress-Induced Leakage Current (SILC), threshold voltage shift observed during Positive Bias Temperature Instability (PBTI) stress, TDDB in various dielectric stacks.     

Effects of electrical leakage currents on MEMS reliability and performance

Electrostatically driven MEMS devices commonly operate with electric fields as high at 10/sup 8/ V/m applied across the dielectric between electrodes. Even with the best mechanical design, the electrical design of these devices has a large impact both on performance (e.g., speed and stability) and on reliability (e.g., corrosion and dielectric or gas breakdown). In this paper, we discuss the reliability and performance implications of leakage currents in the bulk and on the surface of the dielectric insulating the drive (or sense) electrodes from one another. Anodic oxidation of poly-silicon electrodes can occur very rapidly in samples that are not hermetically packaged. The accelerating factors are presented along with an efficient early-warning scheme. The relationship between leakage currents and the accumulation of quasistatic charge in dielectrics are discussed, along with several techniques to mitigate charging and the associated drift in electrostatically actuated or sensed MEMS devices. Two key parameters are shown to be the electrode geometry and the conductivity of the dielectric. Electrical breakdown in submicron gaps is presented as a function of packaging gas and electrode spacing. We discuss the tradeoffs involved in choosing gap geometries and dielectric properties that balance performance and reliability.     

The Ferroelectric Memory and its Applications

The ferroelectric memory is not only an ideal memory with clear advantages such as non-volatility, low power consumption, high endurance and high speed writing, but is also the most suitable device for memory embedded applications. Its manufacturing process makes it more compatible with the standard CMOS process than the traditional non-volatile memory process, since it does not require high voltage operation, and the ferroelectric process does not influence the characteristics of the CMOS devices used in logic cells, analog cells and core cells. In the spreading of Intellectual Property (IP) application for the LSI Industry, this embedded application takes on a more important role. In the near future, the ferroelectric memory technology will be taken into reconfigurable devices as programmable interconnect switches besides being used as embedded memories. These ferroelectric memory based reconfigurable devices can be used as Dynamic Programmable Gate Array (DPGA), which are able to be reconfigured from their original logic in a system under an operation mode. New logic circuits will operated with lower power consumption or a resume function by introducing ferroelectric gated transistors or ferroelectric capacitors. Even though ferroelectric memory technology has many advantages, it is not popular yet, since, the conventional semiconductor process degrades the ferroelectric layer easily. The means to prevent degradation of ferroelectric films in the silicon wafer process will also be discussed.