"可编程逻辑器件及应用"课程的实践教学

本文结合当前"可编程逻辑器件及应用"实践教学的现状,指出进行综合设计创新性实验的必要性.针对该课程实践教学的特点,探讨完成综合设计创新性实验的条件与要求、内容与安排、训练方法与技巧,旨在提高学生的动手能力、实践能力和创新能力.实践证明,取得了较好的教学效果.     

电路可动态重组的模式化综合实验系统的研制

设计了一种基于单片机和可编程逻辑器件的模式化综合实验系统。该实验系统采用电路可动态重组的设计方案,在一套实验系统上既可同时满足"数字电路与逻辑设计"、"可编程逻辑器件与应用"、"单片机原理与应用"三门课程的教学需要,也能完成综合性设计项目。该实验系统共8个模式,预留扩展接口,且EDA核心板和单片机均可根据实际需要进行更换。综合实验系统使用方便、灵活、可升级性好。在实验教学中学生反映良好,极大地提升了教学效果。     

基于FPGA的出租车计程计费器项目教学设计

在高职"可编程逻辑器件技术"的课程教学中,学生对于用硬件描述语言VHDL或Verilog进行复杂系统的设计有一定的难度。文章探讨了以项目化教学模式组织教学,采用EDA工具中的参数化模块库LPM,进行基于可编程逻辑器件FPGA技术的出租车计程计费器的项目教学设计。教学效果表明,学生对FPGA技术的设计流程有了进一步的理解,对FPGA技术的应用能力得到了较大的提高,取得了很好的教学效果。     

基于可编程逻辑器件的数字电路设计

可编程逻辑器件的出现,使得传统的数字系统设计方法发生了根本的改变,所以有必要介绍一下基于可编程逻辑器件的数字电路设计方法.以计数器的实现方法作为实例,介绍了采用原理图和硬件描述语言两种方法作为输入,实现计数器的方法,并描述了编译仿真的方法,给出了对应的仿真结果.采用熟悉的器件为例,使基于可编程逻辑器件的数字电路设计方法更容易理解掌握.     

传统数字设计与FPGA融合的教学改革与实践

本文以兼顾传统逻辑设计和可编程逻辑设计为教学目标,将FPGA融入到数字电子技术实验课程中。通过对课程教学体系和实验教学内容的改革,让学生不仅能对传统基础理论知识进行验证和巩固,并能体会到可编程逻辑器件的灵活性和并行性等特点。实践表明,该教学模式能够较好地解决目前电子技术实验教学体系与行业届的实际应用具有较大偏差的问题,并能有效提高学生的学习兴趣。     

基于CPLD的线阵CCD驱动电路设计与实现

设计和开发了一种线阵CCD驱动电路.该电路主要采用了复杂可编程逻辑器件(CPLD),充分发挥其"可编程"的技术特性,为用户提供了丰富的接口信号.介绍了该驱动电路的主要特性、工作原理和驱动时序的设计思想.实验结果表明:该驱动电路完全满足设计要求,当将其集成到其它测量电路中时,整个测量系统可正常工作,且测量精度满足要求.     

可编程控制器的教学探讨

针对"电工技术"课程中可编程控制器这一章教学中存在的实际问题,提出具体的解决措施.采用与继电接触器系统紧密结合来引入可编程控制器,抓住典型示例介绍可编程控制器的工作原理和方式,并用对电动机的点动控制来突出讲解可编程控制器与继电接触器系统的区别.实践证明,循序渐进的理论教学与设计性实验相配合,是学生学好可编程控制器的有力措施.     

"VLSI设计技术"课程综合实验教学探索

本文探索了"VLSI设计技术"课程的综合实验教学.该课程的实验项目应用了一款电机控制专用集成电路,并由FPGA器件实现.实验内容包含了VLSI设计中的主要电路模块和常用技术.实验提供了自动测试设备(ATE)和电机实验平台两种验证方式供学生自主选择,可以改善学生的学习效果.     

数字集群逻辑控制器测试仪CPLD设计

简要介绍了集群逻辑控制器的功能,并详细阐述了集群逻辑控制器测试系统的重要部分,可编程逻辑器件(CPLD)的设计.设计好的可编程逻辑器件具备同步串口通信的功能,从而使测试系统能够与串行外围接口通信.     

利用可编程器件设计移位寄存器

随着科学技术的发展 ,特别是微电子技术和计算机技术的发展 ,数字逻辑电路的实验手段也不断得到更新、完善和发展。从 80年代中期开始 ,可编程逻辑器件 (PLD)的出现让人们告别了在印刷电路板上拼凑大规模电路的时代。由于可编程逻辑器件与分立逻辑器件相比较具有速度快、容量大、功耗低、可靠性高等众多优点 ,因此被广泛用来取代分立元件逻辑实验。本文介绍一种利用可编程器件设计四位环形移位寄存器的方法。     

基于DNA链置换的三级联组合分子逻辑电路设计

DNA计算研究内容繁多复杂,DNA复杂逻辑电路的搭建属于DNA计算的一个重要研究分支,其中逻辑门的构建属于DNA复杂逻辑电路搭建的基础研究,设计出更为简单的逻辑门可以为研究者搭建复杂电路提供参考,节省基础研究的宝贵时间。针对上述问题,该文利用使能控制端思想,采用DNA链置换技术,设计了与或、与非或非和异或同或3种DNA组合逻辑门。结果显示,设计的3种组合逻辑门可实现6种逻辑运算功能,并利用所构建的组合逻辑门成功构造了多级联组合分子逻辑电路,为DNA计算提供了更多的解决方案,促进了DNA计算机的发展。     

电子技术课程建设探索与实践

电子技术课程由模拟电子技术和数字电路与数字逻辑两门课程组成,是电子信息类专业重要技术基础课。为了解决教学中存在的矛盾,我们在电子技术课程建设中对课程的教学内容、教材建设、教学手段、师资队伍建设等方面进行了深入的改革。本文介绍了浙江工业大学电子技术课程建设的具体做法、取得的成果和主要特色。实践证明,课程建设是提高教学质量、推进素质教育的重要手段。     

"计算机网络"课程教学改革实践

提出了"计算机网络"课程建设的指导思想和措施,对课程教学内容、方法、资源、实验和考核等,进行了全面地设计和改革创新,取得了良好成效,具有借鉴和示范价值.     

A reprogrammable gate array and applications

A field-programmable gate array (FPGA) can implement thousands of gates of logic, has no up-front fixed costs, and can be programmed in a few minutes by writing into on-chip static memory is described. This kind of FPGA can be reprogrammed any number of times, providing a versatile platform for rapid hardware implementation. Reprogrammable technology allows software-like design methodologies to be applied to logic design. The construction of this kind of FPGA, design tradeoffs, and examples of applications that take advantage of reprogrammability are examined     

Undergraduate digital laboratories

Digital circuits are rapidly replacing analog circuits in many areas of electrical engineering. The undergraduate curriculum in electrical engineering has reflected these changes by including more course work in the digital area. The availability of low cost integrated circuit logic elements and minicomputers has made it possible to provide a digital system laboratory program that allows the student to undertake the design of realistic digital systems. This paper discusses the organization of such a laboratory program and the facilities needed to carry out this program.     

Fuzzy fundamentals

An orderly design procedure that can save time and help prevent problems in the development of fuzzy logic systems is presented. The nature of fuzzy logic is examined, and the design of fuzzy control systems is discussed. The architecture of a simple fuzzy controller for a steam turbine is used as an example, to show how fuzzy control models work. A four-step methodology for fuzzy system design is described     

Incremental compilation for parallel logic verification systems

Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the overall ASIC verification flow. In this paper, we describe and analyze a set of incremental compilation steps that can be directly applied to a range of parallel logic verification hardware, including logic emulators. Important aspects of this work include the formulation and analysis of two incremental design mapping steps: the partitioning of newly added design logic onto multiple logic processors and the communication scheduling of newly added design signals between logic processors. To validate our incremental compilation techniques, the developed mapping heuristics have been integrated into the compilation flow for a field-programmable gate-array-based Ikos VirtuaLogic emulator . The modified compiler has been applied to five large benchmark circuits that have been synthesized from register-transfer level and mapped to the emulator. It is shown that our incremental approach reduces verification compile time for modified designs by up to a factor of five versus complete design recompilation for benchmarks of over 100 000 gates. In most cases, verification run-time following incremental compilation of a modified design matches the performance achieved with complete design recompilation.     

Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections

Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other. This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory. The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs, but may also be suitable for use with other detection probability tools and simulation tools.     

Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates

Reversible logic has received much attention in recent years when calculation with minimum energy consumption is considered. Especially, interest is sparked in reversible logic by its applications in some technologies, such as quantum computing, low-power CMOS design, optical information processing and nanotechnology. This article proposes two new reversible logic gates, ZRQ and NC. The first gate ZRQ not only implements all Boolean functions but also can be used to design optimised adder/subtraction architectures. One of the prominent functionalities of the proposed ZRQ gate is that it can work by itself as a reversible full adder/subtraction unit. The second gate NC can complete overflow detection logic of Binary Coded Decimal (BCD) adder. This article proposes two approaches to design novel reversible BCD adder using new reversible gates. A comparative result which is presented shows that the proposed designs are more optimised in terms of number of gates, garbage outputs, quantum costs and unit delays than the existing designs.