A CMOS 0.8-μm transistor-only 1.63-MHz switched-current bandpassΣΔ modulator for AM signal A/D conversion

This paper presents a CMOS 0.8-μm switched-current (SI) fourth-order bandpass ΣΔ modulator (BP-ΣΔM) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z^-1 →-z^-2) to a 1-bit second-order low-pass ΣΔ modulator (LP-ΣΔM). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz     

Quadrature bandpass ΔΣ modulation for digital radio

A quadrature bandpass ΔΣ modulator IC facilitates monolithic digital-radio-receiver design by allowing straightforward “complex A/D conversion” of an image reject mixer's I and Q, outputs. Quadrature bandpass ΔΣ modulators provide superior performance over pairs of real bandpass ΔΣ modulators in the conversion of complex input signals, using complex filtering embedded in ΔΣ loops to efficiently realize asymmetric noise-shaped spectra. The fourth-order prototype IC, clocked at 10 MHz, converts narrowband 3.75-MHz I and Q inputs and attains a dynamic range of 67 dB in 200-kHz (GSM) bandwidth, increasing to 71 and 77 dB in 100- and 30-kHz bandwidths, respectively. Maximum signal-to-noise plus distortion ratio (SNDR) in 200-kHz bandwidth is 62 dB. Power consumption is 130 mW at 5 V. Die size in a 0.8-μm CMOS process is 2.4×1.8 mm²      

A double-sampling pseudo-two-path bandpass ΔΣ modulator

A double-sampling pseudo-two-path bandpass ΔΣ modulator is proposed. This modulator has an output rate equal to twice the clock rate, uses n/2 operational amplifiers (op-amps) for an nth-older noise transfer function, and has reduced clock feedthrough in the signal path band. The required clocks can be simpler to implement than the conventional pseudo-two-path techniques. The measured signal-to-noise ratio and dynamic range of the fourth-order double-sampling pseudo-two-path bandpass ΔΣ modulator in a 30-kHz bandwidth at a center frequency of 2.5 MHz (at a clock frequency of 5 MHz) are 62 and 68 dB, respectively     

Triangularly weighted zero-crossing detector providingΣΔ frequency-to-digital conversion

It is shown that for delta-sigma (ΣΔ) frequency-to-digital conversion (FDC) there is no need for a ΣΔ modulator, since a limited FM signal itself may be considered as an asynchronous ΣΔ bit-stream. By feeding the limited FM signal directly to a sinc² ΣΔ decimator, a triangularly weighted zero-crossing counter FDC is introduced, providing ΣΔ noise shaping. The results measured confirm the theory     

Zero-input oscillation bounds in a bandpass ΣΔmodulator

Sufficient conditions for the state-variables of zero-input oscillations of a bandpass ΣΔ modulator structure to remain within a prescribed square region in the state-space are derived for the full range of parameter values of the digital resonator within the modulator     

A fourth-order bandpass sigma-delta modulator

The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta (ΣΔ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio     

A fourth-order bandpass Δ-Σ modulator usingsecond-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass ΔΣ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-μm CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz     

A 1.8-mW CMOS ΣΔ modulator with integrated mixer forA/D conversion of IF signals

In this paper, the design of a continuous-time baseband sigma-delta (ΣΔ) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF ΣΔ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF ΣΔ modulator is 0.2 mm² in 0.35-μm CMOS     

Design and realization of a digital ΔΣ modulator forfractional-n frequency synthesis

The basic operation of a fractional-n frequency synthesizer has been published, but to date little has been presented on the digital ΔΣ modulators which are required to drive such synthesizers. This paper provides a tutorial overview, which relates digital ΔΣ modulation to other applications of ΔΣ modulation where the literature is more complete. The paper then presents a digital ΔΣ modulator architecture which is economical and efficient and which is practical to realize with commercially available components in comparison with other possible implementations which require extensive custom very large-scale integration (VLSI). A demonstration is made of a 28-b modulator using the architecture presented, which provides a 25-MHz tuning bandwidth and <1-Hz frequency resolution. The modulator is demonstrated in an 800-MHz frequency synthesizer having phase noise of -90 dBC/Hz at a 30-kHz offset     

A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulatorwith 74-dB dynamic range

A 3.3-V bandpass ΣΔ modulator for IF sampling at 10.7 MHz in digital radio applications has been developed. The modulator presents a sixth-order single-loop architecture and features a 74-dB dynamic range in a 2OO-kHz signal bandwidth (FM signal), while for a 9-kHz signal bandwidth (AM signal) the dynamic range is 88 dB. The modulator has been integrated in a standard 0.35-μm CMOS technology using switched-capacitor technique and consumes 76 mW from a single 3.3V supply     

A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dBdynamic range

A CMOS ΣΔ modulator for speech coding with continuous-time loopfilter is presented. Compared to switched-capacitor implementations, the relaxed bandwidth requirements of the active elements of the loopfilter reduce the power consumption. Furthermore, the need for an antialiasing filter at the modulator input is eliminated. A fourth-order, 64× oversampling ΣΔ modulator for application in portable telephones was designed and shows 80 dB dynamic range over the 300-3400 Hz voice bandwidth. Its input is directly connected to the microphone (maximum 40 mV_RMS). Total harmonic distortion (THD) is below -70 dB at 95 μA current consumption from a 2.2 V supply voltage. The active die area of the modulator is 0.5 mm² in a standard 0.5-μm CMOS process     

A two-path bandpass sigma-delta modulator with extended noiseshaping

A three-stage bandpass sigma-delta (ΣΔ) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-μm CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f_s/4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm²     

A 900-mV low-power ΔΣ A/D converter with 77-dB dynamicrange

The design of a low-voltage and low-power ΔΣ analog-to-digital (A/D) converter is presented. A third-order single-loop ΔΣ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV ΔΣ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-μW power consumption     

A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic rangeusing the switched-opamp technique

The design and implementation of a very low supply voltage/low power ΔΣ modulator is presented. It is based on the switched-opamp technique, which allows low voltage operation with a standard process and without voltage multiplication. The design methodology is illustrated with a second-order single-loop ΔΣ modulator. The chip is implemented in a 0.7-μm CMOS process with standard threshold voltages. The power supply is 1.5 V and the power dissipation is only 100 μW. The measured dynamic range in the speech bandwidth of 300-3400 Hz is 12 b. The total harmonic distortion (THD) is lower than -72 dB     

A 80-MHz bandpass ΔΣ modulator for a 100-MHz IFreceiver

A fully differential fourth-order bandpass ΔΣ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-μm CMOS technology and consumes 56 mW from a 3.0-V supply     

Multi-bit cascade ΣΔ modulator for high-speed A/Dconversion with reduced sensitivity to DAC errors

The authors present a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantisation in a cascade architecture to obtain high resolution with a low oversampling ratio. It is less sensitive to the nonlinearity of the digital-to-analogue (DAC) than those previously reported, thus enabling the use of very simple analogue circuitry with neither calibration nor trimming required     

A two-path bandpass ΣΔ modulator for digital IFextraction at 20 MHz

Oversampled bandpass A/D converters based on sigma-delta (ΣΔ) modulation can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals that arise in radios and cellular systems. This paper proposes a two-path architecture for a fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high sampling speeds than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the two-path topology has been integrated in a 0.6-μm, single-poly, triple-metal CMOS technology with capacitors synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz digitize a 200-kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the mixing of spurious tones at DC and f_s/2 with the input appears to degrade the performance of the modulator; out-of-band sinusoidal dither is shown to be an effective means of avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3 V supply     

80 MHz bandpass delta-sigma modulator using switched-capacitorresonator structure

A fully differential 80 MHz fourth-order bandpass ΔΣ modulator, meant for a 100 MHz GSM/WCDMA multimode IF receiver, is presented. The modulator is based on a double-delay single opamp SC-resonator structure which is well suited for low supply voltages. Furthermore, the centre frequency of the topology is insensitive to different component variances. The measured peak SNR is 78 dB and 43.3 dB for 270 kHz (GSM) and 3.84 MHz (WCDMA) bandwidths, respectively     

A CMOS analog front-end circuit for an FDM-based ADSL system

A CMOS analog front-end circuit for an FDM-based ADSL system is presented. The circuit contains all analog functions including AGC amplifiers, continuous-time band pass filters, ΣΔ AD/DA converters, and digital decimation and interpolation filters. On-chip automatic tuning of the bandpass filters provides more than 300% center frequency range with 1% frequency accuracy. The higher-order ΣΔ AD/DA converters achieve 12-b data conversion at 1.54 Msamples/s with an oversampling ratio of only 32. The 0.7 μm CMOS circuit measures 65 mm² and consumes 1.9 W from a single 5 V power supply     

A CMOS monolithic ΔΣ-controlled fractional-N frequencysynthesizer for DCS-1800

A monolithic 1.8-GHz ΔΣ-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-μm CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2×2 mm². To investigate the influence of the ΔΣ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in ΔΣ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints