Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

Effect of oxide resistance on the characterization of interface trap density in MOS structures

The oxide resistance in a practical MOS capacitor is generally not high enough to be negligible in the evaluation of interface trap density based on the qruasi-static capacitance-voltage (C–V) curve. The importance of the effects of oxide resistance ranging from 10¹³ to 10¹⁶ Ω on the C–V curve and the corresponding interface trap density is theoretically shown. To obtain the oxide resistance in MOS structures the newly reported charge-then-decay method is suggested. From the oxide resistance found, one can compare the distribution curves of interface trap density before and after removing the oxide resistance effect. It is found that the results obtained after removing the oxide resistance effect are more consistent than those without removing it. It addition, the removal of the oxide resistance effect for a sample having a hysteresis C–V behavior is also discussed.     

Optoelectronic properties of Zn0.52Se0.48/Si Schottky diodes

Zn_0.52Se_0.48/Si Schottky diodes are fabricated by depositing zinc selenide (Zn_0.52Se_0.48) thin films onto Si(1 0 0) substrates by vacuum evaporation technique. Rutherford backscattering spectrometry (RBS) analysis shows that the deposited films are nearly stoichiometric in nature. X-ray diffractogram of the films reveals the preferential orientation of the films along (1 1 1) direction. Structural parameters such as crystallite size (D), dislocation density (δ), strain (ε), and the lattice parameter are calculated as 29.13 nm, 1.187 × 10⁻¹⁵ lin/m², 1.354 × 10⁻³ lin⁻² m⁻⁴ and 5.676 × 10⁻¹⁰ m respectively. From the I–V measurements on the Zn_0.52Se_0.48/p-Si Schottky diodes, ideality and diode rectification factors are evaluated, as 1.749 (305 K) and 1.04 × 10⁴ (305 K) respectively. The built-in potential, effective carrier concentration (N_A) and barrier height were also evaluated from C–V measurement, which are found to be 1.02 V, 5.907 × 10¹⁵ cm⁻³ and 1.359 eV respectively.     

A circuit-compatible analytical device model for ballistic nanowire transistors

Silicon nanowire transistors (SNWTs) have attracted broad attention as a promising device structure for future integrated circuits. Silicon nanowires with a diameter as small as 2 nm and having high carrier mobility have been achieved. Consequently, to develop TCAD tools for SNWT design and to model SNWT for circuit-level simulations have become increasingly important. This paper presents a circuit-compatible closed-form analytical model for ballistic SNWTs. Both the current–voltage (I–V) and capacitance–voltage (C–V) characteristics are modeled in terms of device parameters and terminal voltages. Such a model can be efficiently used in a conventional circuit simulator like SPICE to facilitate transistor-level simulation of large-scale nanowire or mixed nanowire-CMOS circuits and systems.     

Parallel parasitic conductance in narrow-width MOSFETs

One of the edge effects of narrow-width MOSFETs can be expressed as a parallel parasitic conductance G_P. G_P And the width reduction ΔW were determined from the variation of device's conductance G_T vs mask gate width W_M at different effective gate biases V_GS − V_T. The intersection point of these G_T vs W_M for different V_GS − V_T biases occurs at G_P and ΔW. A series of experiments in which external conductances were placed in parallel with the MOS transistor were performed, and the results verified the concept of the parallel parasitic conductance, and the algorithm for extracting both G_P and ΔW.     

Design optimization of stacked layer dielectrics for minimum gate leakage currents

An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I–V curves are observed for Si₃N₄/SiO₂, Ta₂O₅/SiO₂, Ta₂O₅/SiO_2−yN_y, Ta₂O₅/Si₃N₄, and TiO₂/SiO₂ stacked gates except for Al₂O₃/SiO₂ structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.     

Performances of novel Pd/Sn and Pd/Sn/Au ohmic metallizations to n-GaAs

Performance of novel Pd/Sn and Pd/Sn/Au Ohmic metallizations to n-GaAs have been investigated. Metallizations were deposited using a resistance heating evaporator and annealings were performed utilizing a conventional graphite strip annealer (cGSA). Metallization samples were characterized using scanning tunneling microscopy (STM), secondary ion mass spectrometry (SIMS) and current–voltage (I–V) measurements. Contact resistivities, ρ_c, of the metallizations were measured utilizing conventional transmission line model (cTLM) method. Novel Pd/Sn and Pd/Sn/Au Ohmic contacts exhibit better thermal stability compared to non-alloyed Pd/Ge metallization. In order to investigate the effectiveness of novel Pd/Sn and Pd/Sn/Au Ohmic metallizations in device applications, gallium arsenide metal-semiconductor field-effect transistors (GaAs MESFETs) have been fabricated. MESFETs fabricated with Pd/Sn/Au Ohmic contacts show a extrinsic transconductance, g_me, of more than 133 mS/mm for a gate length, L_G, of 2 μm.     

Frequency dependence of of MOS capacitors

The frequency dependence of ΔV/Δ(C⁻²) of an MOS capacitor, which plays an important role in determining the semiconductor doping profile, is studied theoretically and experimentally. Useful expressions relating the measurable quantities to the doping profile are derived systematically. It is shown how interface states and majority carriers influence the frequency dependence of ΔV/Δ(C⁻²) and give rise to errors in profile determinations. The techniques of measuring the various types of the frequency dependence of ΔV/Δ(C⁻²) are also described.     

On the effect of non-degenerate doping of polysilicon gate in thin oxide MOS-devices—Analytical modeling

A one-dimensional model of the polysilicon-gate-oxide-bulk structure is presented in order to analyze the implanted gate MOS-devices. The influence of the ionized impurity concentration in the polysilicon-gate near the oxide and the charge at the polysilicon-oxide interface on the flat-band voltage, threshold voltage, inversion layer charge and the quasi-static C–V characteristic is quantitatively studied. The calculations show a considerable degradation of the inversion layer charge due to the voltage drop in the gate, especially in thin oxide devices. The calculated quasi-static C–V curves agree with the recently published data of implanted gate devices.     

A novel linearly tunable butterfly-shape MEMS capacitor

A new MEMS tunable capacitor with linear capacitance–voltage (C–V) response is introduced. The design is developed based on a parallel-plate configuration and uses the structural lumped flexibility and geometry optimization to obtain a linear response. The moving electrode is divided into two segments connected to one another by a torsional spring. There are extra beams located between the two plates, which constrain the displacement of the moving plate. The resulting nonlinear structural rigidity provides the design with higher tunability than the parallel-plate ones. Furthermore, because the plate's displacement is controlled, the shape of C–V curve changes in such a way that high linearity is achieved. The proposed design can be fabricated by a three-structural-layer process such as PolyMUMPs. The results of analytical solution and experimental measurements verify that the new capacitor can produce tunability of over 100% with high linearity. The introduced design methodology can further be extended to flexible plates and beams to obtain smooth C–V curves.     

An analytical model for the power bipolar-MOS transistor

This paper presents an analytical model for the I–V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4–10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in V_F. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase V_F but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.     

Simulation and experimental results on the forward J–V characteristic of Al implanted 4H–SiC p–i–n diodes

In this work the forward J–V characteristics of 4H–SiC p–i–n diodes are analysed by means of a physics based device simulator tuned by comparison to experimental results. The circular devices have a diameter of 350 μm. The implanted anode region showed a plateau aluminium concentration of 6×10¹⁹ cm⁻³ located at the surface with a profile edge located at 0.2 μm and a profile tail crossing the n-type epilayer doping at 1.35 μm. Al atom ionization efficiency was carefully taken into account during the simulations. The final devices showed good rectifying properties and at room temperature a diode current density close to 370 A/cm² could be measured at 5 V. The simulation results were in good agreement with the experimental data taken at temperatures up to about 523 K in the whole explored current range extending over nine orders of magnitude. Simulations also allowed to estimate the effect of a different p⁺ doping electrically effective profile on the device current handling capabilities.     

High stability and low driving voltage green organic light emitting diode with molybdenum oxide as buffer layer

Green organic light emitting diodes (OLEDs) with copper phthalocyanine (CuPc), 4,4′,4″-tris[3-methylphenyl(phenyl)amino]triphenymine (m-MTDATA) and molybdenum oxide (MoO_x) as buffer layers have been investigated. The MoO_x based device shows superior performance with low driving voltage, high power efficiency and much longer lifetime than those with other buffer layers. At the luminance of 100 cd/m², the driving voltage is 3.8 V, which is 0.5 V and 2.2 V lower than that of the devices using CuPc (Cell-CuPc) and m-MTDATA (Cell-m-MTDATA) as buffer layer, respectively. Its power efficiency is 13.6 Lm/W, which is 38% and 30% higher than that of Cell-CuPc and Cell-m-MTDATA, respectively. The projected half-life under the initial luminance of 100 cd/m² is 42,400 h, which is more than 3.8 times longer than that of Cell-m-MTDATA and 24 times that of Cell-CuPc. The superior performance of Cell-MoO_x is attributed to its high hole injection ability and the stable interface between MoO_x and organic material. The work function of MoO_x measured by contact potential difference method and the J–V curves of “hole-only” devices indicate that a small barrier between MoO_x/N,N′-di(naphthalene-1-y1)-N,N′-dipheyl-benzidine (NPB) leads to a strong hole injection, resulting in the low driving voltage and the high stability.     

Novel structure of GaAs-based interdigital-gated HEMT plasma devices for solid-state THz wave amplifier

Theoretical analysis of potential distribution in the interdigital-gated high electron mobility transistor (HEMT) plasma wave device was carried out. The dc I–V characteristics of capacitively coupled interdigital structure showed that uniformity of electric field under the interdigital gates was improved compared to the dc-connected interdigital gate structure. Admittance measurements of capacitively coupled interdigital gate structure in the microwave region of 10–40 GHz showed the conductance modulation by drain–source voltage. These results indicate the existence of plasma wave interactions.     

A complete analytical model of GaN MESFET for microwave frequency applications

A simple physics-based analytical model for a non-self-aligned GaN MESFET suitable for microwave frequency applications is presented. The model includes the effect of parasitic source/drain resistances and the gate length modulation. The model is then extended to evaluate I–V and C–V characteristics, transconductance, cut-off frequency, transit time, RC time constant, optimum noise figure and maximum power density. The transconductance of about 21 mS/mm is obtained for GaN MESFET using the present theory in comparison to 23 mS/mm of the reported data. The cut-off frequency of more than 1 GHz, optimum noise figure of 6 dB and maximum output power density of more than 1 W/mm are predicted.     

Design and fabrication of multiple-valued multiplexer using negative differential resistance circuits and standard SiGe process

The design of a four-valued multiplexer using the negative differential resistance (NDR) circuit is demonstrated. The NDR circuit used in this work is made of the Si-based metal–oxide–semiconductor field-effect-transistor (MOS) and the SiGe-based heterojunction bipolar transistor (HBT). However we can obtain the NDR characteristic in its combined I–V curve by suitably arranging the MOS parameters. This novel multiplexer is made of MOS–HBT–NDR-based decoders and inverters. The fabrication is based on the standard 0.35 μm SiGe BiCMOS process.     

A novel silicide nanopatterning method for the fabrication of ultra-short channel Schottky-tunneling MOSFETs

A novel nanometer patterning technique was developed to pattern epitaxial CoSi₂ layers and to fabricate Schottky-tunneling MOSFETs. The nanopatterning method is based on the local oxidation of silicide layers. A feature size as small as 50 nm was obtained for 20 nm epitaxial CoSi₂ layers on Si(100) after patterning by local rapid thermal oxidation in dry oxygen. A Schottky-tunneling MOSFET with epitaxial CoSi₂ Schottky contacts at both the source and the drain was fabricated using this nanopatterning method to make the 100 nm gate. The device shows good I–V characteristics at 300 K.     

Breakdown degradation associated with elementary screw dislocations in 4H-SiC pn junction rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector>2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector=1c with no hollow core) in densities on the order of thousands per cm², nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current–voltage (I–V) characteristics of 4H-SiC p⁺n diodes. First, synchrotron white beam X-ray topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p⁺n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I–V knee, and no visible concentration of breakdown current. In contrast, devices that contained at least one elementary screw dislocation exhibited 5–35% reduction in breakdown voltage, a softer breakdown I–V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.     

Electrical properties of W/Si interfaces with embedded Ge/Si islands

In this work, we investigated electrical and morphological properties of W/p-type Si Schottky diodes with intentional inhomogeneities introduced by macroscopic Ge-islands embedded beneath the interface. The Si-cap layer thickness (or the island-distance to the interface) was progressively reduced by successive chemical etching cycles. Electrical characterizations were achieved through reverse current–voltage (I–V) at room temperature and forward I–V measurements as a function of the temperature. In parallel, Rutherford backscattering spectroscopy analyses were performed to follow the Si-cap/Ge islands chemical thinning down with increasing the number of etching cycles. In addition, the comparison of topographical and electrical properties of the etched silicon-cap layer was carried out by conductive atomic force microscopy analyses with a nanometer-scale resolution. Our results indicate that the areas on the top of islands exhibit lower resistance than those which covered the wetting layer. This lateral variation of resistance at the surface of the semiconductor may correspond to Schottky barrier height inhomogeneities observed on broad area I–V characteristics of Schottky contacts.     

An a-SiGe:H phototransistor integrated with a Pd film on glasssubstrate for hydrogen monitoring

A novel a-SiGe:H optoelectronic hydrogen gas sensing device has been developed. The optoelectronic gas sensing device integrated a high optical gain a-SiGe:H optical sensor with a sputtered palladium (Pd) film on a glass substrate. Through the mechanism of the Pd film's transmitted optical power modulated with the H₂ concentration in atmosphere, the device can be operated at room temperature with a wider range (50 ppm to 133000 ppm) and faster response, in comparison to a conventional Pd catalytic type H₂ sensors, thus providing a good candidate for hydrogen monitoring