CORDIC算法的FPGA与DSP实现的优劣分析

介绍了坐标旋转数字计算机（CORDIC）的算法原理,分析了算法中旋转迭代次数、操作数位宽与精度的关系,在现场可编程门阵列（FPGA）芯片和数字信号处理器（DSP）芯片上用全流水、高并行结构分别实现了旋转模式下的CORDIC算法,并将两者的精度、时间效率、空间效率的优劣进行比较。结果表明,DSP数值精度比FPGA高且设计更灵活,可移植性更强;而FPGA速度远远快于DSP,消耗硬件资源更少。     

A system for systolic modules for the MUSIC algorithm

The authors believe that special-purpose architectures for digital signal processing (DSP) real-time applications will use closely coupled processing elements as array processor modules to implement the various portions of the new algorithms, and several such modules will cooperate in a pipelined manner to implement complete algorithms. Such an architecture, based upon systolic modules, for the MUSIC algorithm is presented. The architecture is suitable for VLSI implementation. The throughput of the pipelined approach is O(N), whereas the sequential approach is O(N³)     

Mixed-radix,virtually scaling-free CORDIC algorithm based rotator for DSP applications

In this work, we proposed a novel Coordinate Rotation DIgital Computer (CORDIC) rotator algorithm that converges faster by performing radix-2,4 and 16 CORDIC iterations while maintaining the scale factor implicitly constant. A mixed-radix is used to achieve convergence faster to reduce the computational latency of the CORDIC algorithm. The main concern of the higher radix CORDIC algorithm is the compensation of a variable scale factor. To solve this problem, the Taylor series approximation of sine and cosine is proposed for a higher radix CORDIC algorithm to achieve the scaling-free rotation of the two-dimensional vector. The scaling-free rotation of the proposed CORDIC algorithm removes the read-only memory (ROM) needed to store scale factor of higher radix CORDIC algorithm. Further, the proposed CORDIC algorithm is designed in rotation mode and optimized by removing the Z datapath for the digital signal processing (DSP) applications for which the angle of rotation is known in advance. Finally, the multipath delay commutator (MDC) fast Fourier transform (FFT) algorithm is implemented with the proposed CORDIC algorithm based rotator on FPGA. The proposed design is compared with existing designs. In a comparison between the radix-16 CORDIC rotator based FFT implementation and our proposed implementation, it has been found out that implementation proposed in this article has used 17% fewer resources.     

A scaled DCT architecture with the CORDIC algorithm

This paper presents an efficient approach for computing the N-point (N=2ⁿ) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture     

CORDIC-lifting factorization of paraunitary filter banks based on the quaternionic multipliers for lossless image coding

Quaternions have offered a new paradigm to the signal processing community: to operate directly in a multidimensional domain. We have recently introduced the quaternionic approach to the design and implementation of paraunitary filter banks: four- and eight-channel linear-phase paraunitary filter banks, including those with pairwise-mirror-image symmetric frequency responses. The hypercomplex number theory is utilized to derive novel lattice structures in which quaternion multipliers replace Givens (planar) rotations. Unlike the conventional algorithms, the proposed computational schemes maintain losslessness regardless of their coefficient quantization. Moreover, the one regularity conditions can be expressed directly in terms of the quaternion lattice coefficients and thus easily satisfied even in finite-precision arithmetic. In this paper, a novel approach to realizing CORDIC-lifting factorization of paraunitary filter banks is presented, which is based on the embedding of the CORDIC algorithm inside the lifting scheme. Lifting allows for making multiplications invertible. The 2D CORDIC engine using sparse iterations and asynchronous pipeline processor architecture based on the embedded CORDIC engine as stage of processor is reported. Also it is necessary to notice, that the quaternion multiplier lifting scheme based on the 2D CORDIC algorithm is the structural decision for the lossless digital signal processing. This approach applies to very practical filter banks, which are essential for image processing, and addresses interesting theoretical questions.     

Parallel singular value decomposition of complex matrices usingmultidimensional CORDIC algorithms

The singular value decomposition (SVD) of complex matrices is computed in a highly parallel fashion on a square array of processors using Kogbetliantz's analog of Jacobi's eigenvalue decomposition method. To gain further speed, new algorithms for the basic SVD operations are proposed and their implementation as specialized processors is presented. The algorithms are 3-D and 4-D extensions of the CORDIC algorithm for plane rotations. When these extensions are used in concert with an additive decomposition of 2×2 complex matrices, which enhances parallelism, and with low resolution rotations early on in the SVD process, which reduce operation count, a fivefold speedup can be achieved over the fastest alternative approach     

采用CORDIC算法的直接数字频率合成器的设计

为了实现CORDIC（Coordinate Rotation Digital Computer）算法在DDS（Direct Digital Frequency Synthesis）中的应用,文章介绍了CORDIC算法的一般法则和DDS的基本结构,提出了一种流水线型的CORDIC算法,并应用于FPGA（Field Programmable Gate Array）设计中,最后给出了基于ModelSim的仿真结果。     

一种新型的用于数字信号处理的进化硬件原胞结构

采用CORDIC算法在单一的电路体系结构下实现了具有多种算术功能的进化电路原胞。该原胞可以作为构建此类进化硬件的基本组成模块。分析表明,采用CORDIC算法的原胞具有丰富的运算能力而只消耗较少的芯片资源,可以成为一种有前途的用于数字信号处理功能级进化电路的原胞设计的方案。     

Instruction Set Extensions for Matrix Decompositions on Software Defined Radio Architectures

Emerging wireless applications consistently demand higher data rates. Unfortunately, it is challenging to achieve high data rates within the limited amount of available frequency spectrum. Hence, enhanced spectral efficiency and link reliability within the available frequency spectrum are of the utmost importance in current and next generation wireless protocols. To attain high spectral efficiency and link reliability, wireless protocols employ increasingly complex 2-dimensional techniques that involve computationally-intensive matrix operations. Multiple-Input Multiple-Output (MIMO) communication is an example of a promising technique employed by wireless protocols to deliver higher data rates at the cost of increased algorithmic complexity. Application Specific Integrated Circuits (ASICs) have traditionally been used to implement compute-intensive wireless protocols. The wireless industry has been gradually moving towards an alternative programmable platform called Software Defined Radio (SDR) due to its significant benefits, such as reduced development costs, and accelerated time-to-market. The computationally-intensive matrix operations used in current and next generation wireless protocols are extremely expensive to implement in SDR platforms with conventional Digital Signal Processor (DSP) instruction sets. Hence there is a need for novel instructions, hardware designs and algorithm enhancements to enable higher spectral efficiency on SDR platforms. In this paper, we propose Single Instruction Multiple Data (SIMD) CoOrdinate Rotation DIgital Computer (CORDIC) instruction set extensions with CORDIC hardware support to speedup computationally-intensive matrix decomposition algorithms. The CORDIC instruction set extensions have been implemented on the Sandbridge Sandblaster SB3000 SDR platform and evaluated on conventional algorithms used for decomposing a closed loop 4-by-4 Worldwide Interoperability for Microwave Access (WiMAX) MIMO channel into independent Single-Input Single-Output (SISO) channels. Our experimental results on the closed-loop MIMO channel decomposition using CORDIC instructions demonstrate more than 6x speedup over a Sandblaster baseline implementation that uses state-of-the-art SIMD DSP instructions. The CORDIC instructions also provide similar numerical accuracy when compared to the baseline implementation. The techniques we propose in this paper are also applicable to other SDR and embedded processor architectures.     

基于FPGA的DBF导向矢量实时算法

针对某相控阵雷达的数字波束形成[1]的导向矢量计算,提出了一种基于FPGA的较为灵活的实时算法。利用CORDIC核及流水累加运算,在保证高精度计算的前提下,克服了以往查表带来的资源浪费与不便,直接根据天线阵元间距、波束指向和工作频率就可实时完成系统对波束形成的导向矢量的求取。     

基于CORDIC算法的数字下变频器设计

数字下变频技术的基本功能是将宽带高速数据流信号转变成窄带低速数据流信号,以便DSP实时处理。研究了基于协调旋转数字式计算机(CORDIC)算法的数字下变频设计,这种方法能有效提高信号处理效率,减小硬件设计的代价,并且通过仿真证明该方法的高效性。     

Digit-pipelined direct digital frequency synthesis based on differential CORDIC

A novel direct digital frequency synthesis (DDFS) architecture based on the differential CORDIC (DCORDIC) algorithm is presented. The architecture allows digit-level pipelining in the CORDIC angle path by implementing a two-dimensional systolic array. Unlike other DDFS architectures, it incorporates the phase accumulator in the digit-level pipelining framework so that a bottleneck-free datapath throughout the whole system is achieved in a scalable manner. A generic environment that generates fully synthesizable Verilog codes that implement the proposed architecture is created and the physical attributes of the resulting system are discussed.     

CORDIC algorithm based digital detection technique applied in resonator fiber optic gyroscope

A digital detection technique based on the coordinate rotation digital computer (CORDIC) algorithm is proposed for a resonator fiber optic gyroscope (R-FOG). It makes the generation of modulation signal, synchronous demodulation and signal processing in R-FOG to be realized in a single field programmable gate array (FPGA). The frequency synthesis and synchronous detection techniques based on the CORDIC algorithm have been analyzed and designed firstly. The experimental results indicate that the precision of the detection circuit satisfies the requirements for the closed-loop feedback in R-FOG system. The frequency of the laser is locked to the resonance frequency of the fiber ring resonator stably and the open-loop gyro output signal is observed successfully. The dynamic range and the bias drift of the R-FOG are ±1.91 rad/s and 0.005 rad/s over 10 s, respectively.     

Carry-save architectures for high-speed digital signal processing

Carry-save arithmetic, well known from multiplier architectures, can be used for the efficient CMOS implementation of a much wider variety of algorithms for high-speed digital signal processing than, only multiplication. Existing architectural strategies and circuit concepts for the realization of inner-product based and recursive algorithms are recalled. The two's complement overflow behavior of carry-save arithmetic is analyzed and efficient overflow correction schemes are given. Efficient approaches are presented for the carry-save, implementation of a saturation control. The concepts are extended and refined for the high-throughput implementation of decisiondirected algorithms such as division, modulo multiplication and CORDIC which have yet been avoided because of a lack of efficient concepts for implementation.It is shown, that the carry-save technique can be extended to a comprehensive method to implement high-speed DSP algorithms. Successfully fabricated commercial VLSI circuits emphasize the potential of this method.     

基于CORDIC算法的数字中频检波技术研究

为了解决模拟包络检波器受温度影响大、测试精度不高且丢失相位信息等问题,提出了一种基于CORDIC算法的数字中频检波方案,完成幅度、相位及频率检测功能.首先讨论了数字检波的工作原理,分析了其数学模型,然后给出了基于CORDIC算法的幅度和相位检测方案,并在数字鉴相基础上,介绍了使用一阶差分结构实现数字鉴频的方法,同时分析了差分鉴频中出现的相位模糊问题,给出了如何提高鉴频精度的方法.最后,使用FPGA实现了基于CORDIC算法的数字检波器.通过计算机仿真和应用实例表明,基于CORDIC算法的数字中频检波方案是可行的,并且可以获得较高的测量精度.     

基于折叠变换的CORDIC算法实现

在现代数字信号处理领域中,CORDIC算法是一种重要的数学计算方法。该算法采用一种迭代的方式,运算简便,被广泛应用于乘除法、开方以及一些三角函数运算当中。但CORDIC算法需要较高的迭代级数以保证运算精度,在进行FPGA实现时仍然会消耗较多的硬件逻辑资源。为进一步减少CORDIC算法实现时的资源消耗,设计并实现了一种基于折叠变换的CORDIC算法。相比传统的流水结构CORDIC算法,该折叠结构的CORDIC算法消耗的硬件资源大大减少。文中给出了这一方法的实现结构,并给出了仿真结果。     

行为级DSP算法描述的阵列处理器综合方法研究

本文提出了针对递归DSP算法的高层次系统综合流程,并以脉动(systolic)式处理器阵列结构实现.从DSP算法的FDDL行为级描述开始,经由编译及划分,产生数据相关流图(Data Dependency Graph),然后实现对算法流图的空间映射及时域规划,得到算法的信号流图(Signal Flow Graph),经时序重构,生成脉动阵列,最后实现对处理器单元的数据路径综合及控制器综合,并对处理器单元定位,本文同时提出了各设计阶段的算法策略及优化策略,并给出综合结果。     

基于System Generator的 CORDIC算法DDS的FPGA实现

基于DDS(直接数字频率合成器)的原理,采用XILINX公司的软件system generator,搭建了基于CORDIC算法的全流水线DDS系统,它不仅比传统查找表式的DDS系统节省了大量存储器资源,达到较高的运算速度,而且利用较新的DSP工具实现了系统的快速设计。     

Configurable logic for digital communications: some signalprocessing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies     

Active noise control: a tutorial review

Active noise control (ANC) is achieved by introducing a cancelling “antinoise” wave through an appropriate array of secondary sources. These secondary sources are interconnected through an electronic system using a specific signal processing algorithm for the particular cancellation scheme. ANC has application to a wide variety of problems in manufacturing, industrial operations, and consumer products. The emphasis of this paper is on the practical aspects of ANC systems in terms of adaptive signal processing and digital signal processing (DSP) implementation for real-world applications. In this paper, the basic adaptive algorithm for ANC is developed and analyzed based on single-channel broad-band feedforward control. This algorithm is then modified for narrow-band feedforward and adaptive feedback control. In turn, these single-channel ANC algorithms are expanded to multiple-channel cases. Various online secondary-path modeling techniques and special adaptive algorithms, such as lattice, frequency-domain, subband, and recursive-least-squares, are also introduced. Applications of these techniques to actual problems are highlighted by several examples