The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

Study on hydrogenation of polysilicon thin film transistors by ionimplantation

Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H⁺ dose of 5×10¹⁵ cm^-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm ²/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at V_DS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation     

High-performance p-channel poly-Si TFT's using electron cyclotronresonance hydrogen plasma passivation

This letter presents a summary of the first detailed investigation of electron cyclotron resonance (ECR) hydrogen plasma exposure treatments of p-channel poly-Si thin film transistors (TFT's). It is shown that ECR hydrogenation can be much more efficient than RF hydrogenation. Poly-Si p-channel TFT's fabricated at low temperatures (⩽625°C) and passivated with the ECR hydrogenation treatment are shown to exhibit ON/OFF current ratios of 7.6×10⁷, subthreshold swings of 0.62 V/decade, threshold voltages of -4.6 V, and hole mobilities over 18 cm²/V.s     

The impact of oxidation of channel polysilicon on the trap-densityof submicron bottom-gate TFT's

Oxidation of channel polysilicon improves characteristics of narrow channel TFT's, especially in leakage current. Small leakage current of less than -20 fA/μm and high on/off ratio of about 7 orders of magnitude at a drain voltage of -3.3 V have been achieved by this method. By the analysis of trap densities, leakage current reduction in the oxidized TFT is attributed to the oxidation encroachment under the channel polysilicon which results in a decrease of interface-state density from 5×10¹¹/cm² to about 10¹⁰/cm² at both gate side and back side of the channel polysilicon. It is pointed out that interface state is in some cases more responsible for device degradation than bulk traps and that the reduction of interface states is indispensable to improving device characteristics. This method is directly applicable to TFT load SRAM's in which TFT width is less than 0.5 μm     

Low-cost process for fabricating polysilicon transistors

A process for the fabrication of p-channel polysilicon MOS transistors is described. The process is compatible with the use of low-temperature glass substrates and replaces the use of ion implantation for the source/drain doping with in situ doped polysilicon. MOS transistors made with this process exhibit an on/off current ratio of 2.5×10⁵, a mobility of 16 cm²/V-s, and a subthreshold slope of 1.3 V/decade     

Impact of nitrogen (N14) implantation into polysilicongate on high-performance dual-gate CMOS transistors

The effect of nitrogen (N₁₄)implant into dual-doped polysilicon gates was investigated. The electrical characteristics of sub-0.25-μm dual-gate transistors (both p- and n-channel), MOS capacitor quasi-static C-V curve, SIMS profile, poly-Si gate R_s , and oxide Q_bd were compared at different nitrogen dose levels. A nitrogen dose of 5×10¹⁵ cm^-2 is the optimum choice at an implant energy of 40 KeV in terms of the overall performance of both p- and n-MOSFETs and the oxide Q_bd. The suppression of boron penetration is confirmed by the SIMS profiles to be attributed to the retardation effect in bulk polysilicon with the presence of nitrogen. High nitrogen dose (1×10¹⁶ cm^-2) results in poly depletion and increase of sheet resistance in both unsilicided and silicided p⁺ poly, degrading the transistor performance. Under optimum design, nitrogen implantation into poly-Si gate is effective in suppressing boron penetration without degrading performance of either p- or n-channel transistors     

Impact of nitrogen (N2+) implantation intopolysilicon gate on thermal stability of cobalt silicide formed onpolysilicon gate

A novel process which uses N₂⁺ implantation into polysilicon gates to suppress the agglomeration of CoSi₂ in polycide gated MOS devices is presented. The thermal stability of CoSi₂/polysilicon stacked layers can be dramatically improved by using N₂⁺ implantation into polysilicon. The sheet resistance of the samples without N₂⁺ implantation starts to increase after 875°C RTA for 30 s, while the sheet resistance of CoSi₂ film is not increased at all after 950 and 1000°C RTA for 30 s if the dose of nitrogen is increased up to 2×10¹⁵ cm^-2 and 6×10¹⁵ cm², respectively, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed. It is found that the transformation to CoSi₂ from CoSi is impeded by N₂⁺ implantation such that the grain size of CoSi₂ with N₂⁺ implantation is much smaller than that without N₂⁺ implantation. As a result, the thermal stability of CoSi₂ is significantly improved by N₂⁺ implantation into polysilicon     

Effects of trap-state density reduction by plasma hydrogenation inlow-temperature polysilicon TFT

The reduction of trap-state densities by plasma hydrogenation in n-channel polysilicon thin-film transistors (poly-TFTs) fabricated using a maximum temperature of 600°C has been studied. Hydrogenated devices have a mobility of ~40 cm²/V×5, a threshold voltage of ~2 V, an inverse subthreshold of ~ 0.55 V/decade, and a maximum on/off current ratio of 5×10⁸. The effective channel length decreases by ~0.85 μm after a short hydrogenation which may be attributed to the activation of donors at trap states near the source/drain junctions. Trap-state densities decrease from 1.6×10¹² to 3.5×10¹¹ cm^-2 after hydrogenation, concomitant with the reduction of threshold voltage. Using the gate lengths at which the trap-state densities deviate from the long-channel values as markets for the leading edge of passivation, the apparent hydrogen diffusivity is found to be 1.2×10^-11 cm²/s at 350°C in the TFT structure     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

Advanced TFT SRAM cell technology using a phase-shift lithography

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 μm to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFT's for load devices. The effect of the Si₃N₄ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6×10⁶ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns     

High-performance EEPROMs using N- and P-channel polysiliconthin-film transistors with electron cyclotron resonanceN2O-plasma oxide

High-performance EEPROMs using n- and p-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) N₂O-plasma oxide have been demonstrated. Both programming and erasing were accomplished by Fowler-Nordheim (F-N) tunneling within 1 ms regardless of programming and erasing voltages. The poly-Si TFT EEPROMs have a threshold voltage shift of 4 V between programmed and erased states; furthermore, they maintain a large threshold voltage shift of 2.5 V after 1×10⁵ program and erase cycles. This is attributed to the excellent charge-to-breakdown (Qbd) up to 10 C/cm² of ECR N₂O-plasma oxide     

High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

Design study of AlGaAs/GaAs HBTs

The frequency performance of AlGaAs/GaAs heterojunction bipolar transistors (HBTs) having different layouts, doping profiles, and layer thicknesses was assessed using the BIPOLE computer program. The optimized design of HBTs was studied, and the high current performances of HBTs and polysilicon emitter transistors were compared. It is shown that no current crowding effect occurs at current densities less than 1×10⁵ A/cm² for the HBT with emitter stripe width S_E<3 μm, and the HBT current-handling capability determined by the peak current-gain cutoff frequency is more than twice as large as that of the polysilicon emitter transistor. An optimized maximum oscillation frequency formula has been obtained for a typical process n-p-n AlGaAs/GaAs HBT having base doping of 1×10 ¹⁹ cm^-3     

Polysilicon emitter p-n-p transistors

In-situ boron-doped polysilicon has been used to form the emitter in p-n-p transistors. Various polysilicon deposition conditions, interface preparation treatments prior to deposition, and post-deposition anneals were investigated. Unannealed devices lacking a deliberately grown interfacial oxide gave effective emitter Gummel numbers G_E of 7-9×10^-12s cm^-4 combined with emitter resistances R_E of approximately 8 μΩcm². Introduction of a chemically grown interfacial oxide increased G_E to 2×10 ¹⁴s cm^-4, but also raised R_E by a factor of three. Annealing at 900°C following polysilicon deposition raised G_E values for transistors lacking deliberate interfacial oxide to approximately 6×10¹³s cm^-4, but had little effect of G_E for devices with interfacial oxide. Both types of annealed devices gave R_E values in the range 1-2 μΩcm²     

Modeling the variation of the low-frequency noise in polysiliconemitter bipolar junction transistors

The variation of the low-frequency noise in polysilicon emitter bipolar junction transistors (BJTs) was investigated as a function of emitter area (A_E). For individual BJTs with submicron-sized A _E, the low-frequency noise strongly deviated from a 1/f-dependence. The averaged noise varied as 1/f, with a magnitude proportional to A_E^-1, while the variation in the noise level was found to vary as A_E^-1.5. A new expression that takes into account this deviation is proposed for SPICE modeling of the low-frequency noise. The traps responsible for the noise were located at the thin SiO₂ interface between the polysilicon and monosilicon emitter. The traps' energy level, areal concentration and capture cross-section were estimated to 0.31 eV, 6×10⁸ cm^-2 and 2×10^-19 cm ², respectively     

High performance low temperature polysilicon thin film transistorusing ECR plasma thermal oxide as gate insulator

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (⩽600°C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm²/V·s for n-channel and 69 (48) cm²/V·s for p-channel respectively when using Si₂ H₆(SiH₄) source gas for the deposition of active poly-Si films     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

The effects of fluorine passivation on polysilicon thin-filmtransistors

The fluorine implantation on polysilicon was found to improve the characteristics of polysilicon thin-film transistors (TFT's). The fluorine passivates the trap states within the polysilicon channel, as compared with the H₂-plasma passivation. The fluorine implantation passivates more uniformly both the band tail-states and midgap deep-state, while the H₂-plasma treatment is more effective to passivate deep states than tail states. A fluorine-implanted device can be further improved its performance if an H₂-plasma treatment is applied. In contrast to the H₂ -plasma passivation, the fluorine passivation improves the device hot-carrier immunity. Combining the fluorine passivation and H₂ -plasma passivation, a high performance TFT with a high hot-carrier immunity can be obtained