Low-temperature polysilicon thin-film transistors fabricated fromlaser-processed sputtered-silicon films

In an effort to develop a simple low-temperature high-performance polysilicon thin-film transistor (TFT) technology, we report a fabrication process featuring laser-crystallized sputtered-silicon films. This top Al-gate coplanar TFT process subjects the substrate to a maximum temperature of 300°C, and produces devices with mobilities up to 450 cm²/Vs, on/off current ratios greater than 10⁷ , without using a post-hydrogenation step. We believe these results represent the highest performance TFT's to date fabricated from sputtered silicon films     

Tenth-micron polysilicon thin-film transistors

Small thin-film polysilicon transistors are of interest for load devices in static random-access memory (SRAM) cells of the near future. We present measured characteristics of thin-film transistors (TFT's) with gate lengths ranging from 7 to 0.12 μm made in large-grain polysilicon     

High-performance laser-processed polysilicon thin-film transistors

We present electrical results from hydrogenated laser-processed polysilicon thin-film transistors (TFT's) fabricated using a simple four-mask self-aligned aluminum top-gate process. Transistor field-effect mobilities of 280-450 cm²/Vs and on/off current ratios of more than 10⁸ are measured in these devices. Except for the amorphous-silicon deposition step, the highest processing temperature that the substrate was subjected to was 350°C. Such good performance is attributed to an optimized laser-crystallization process combined with hydrogenation     

Avalanche-induced effects in polysilicon thin-film transistors

A comparison of experimental data and two-dimensional numerical simulations of polysilicon thin-film transistors (TFTs) is presented. It is shown that avalanche multiplication causes both the kink effect in the output characteristics and the reduction of threshold voltage in short-channel device. It is shown that exactly the same physical model for avalanche multiplication gives very good agreement between simulations and experimental data for both these effects. It is demonstrated that it is the presence of grain boundaries or traps in the polysilicon that causes avalanche effects to be much greater than in comparable single-crystal silicon devices     

Characteristics of thin film transistors fabricated in polysilicon films deposited by plasma enhanced chemical vapor deposition

Thin-film transistors (TFTs) fabricated in polysilicon films deposited by plasma enhanced chemical vapor deposition (PECVD) were characterized. The transistors were fabricated using a low temperature process (i.e., <- 700° C). The characteristics of the devices were found to improve as the deposition temperature of the polysilicon film increased. The best characteristics (μ _FE of 15 cm²/V _s andV _TH of 2.2V) were measured in the devices fabricated in the film deposited at 700° C. The devices fabricated in the PECVD polysilicon films were compared to those fabricated in polysilicon films deposited by thermal CVD in the same reactor in order to decouple the effect of the plasma. A coplanar electrode structure TFT with adequate characteristics (μ _FE of 8 cm²/V _s) was also demonstrated in the PECVD polysilicon films.     

Floating body effects in polysilicon thin-film transistors

Floating body effects in polycrystalline silicon thin film transistors (poly-TFTs) are investigated by means of numerical simulations. The current increase in the output characteristics at large V_DS, usually referred to as the “kink effect” is explained by impact ionization occurring in the high-field region at the drain end of the channel. Its effect is enhanced by the action of a parasitic bipolar transistor in the back-channel region, whose base current arises from the impact generated holes. The dependence of the kink on the recombination kinetics is also investigated     

Performance enhancement of offset gated polysilicon thin-film transistors

Simple offset gated n-channel polysilicon thin film transistors (TFTs) of channel length L=10 /spl mu/m were investigated in relation to the intrinsic offset length /spl Delta/L and the polysilicon quality. For /spl Delta/L/spl les/1 /spl mu/m, the device parameters such as threshold voltage, subthreshold slope and field effect mobility are improved, while the leakage current remains unchanged. In TFTs with /spl Delta/L>1 /spl mu/m, the leakage current decreases with increasing the offset length. When the polysilicon layer is of high quality (large grain size and low intra-grain defect density), the leakage current is completely suppressed without sacrificing the on-current in TFT's with offset length of 2 /spl mu/m.     

Self-aligned aluminum top-gate polysilicon thin-film transistorsfabricated using laser recrystallization and gas-immersion laser doping

We present electrical results from polysilicon thin film transistors (TFT's) fabricated using laser-recrystallized channels and gas-immersion laser-doped source-drain regions. A simple, four-level self-aligned aluminum top-gate process is developed to demonstrate the effectiveness of these laser processes in producing TFT's. The source-drain doping process results in source-drain sheet resistances well below 100 Ω/□. TFT field-effect mobilities in excess of 200 cm²/Vs are measured for the laser-fabricated unhydrogenated TFT's     

Analysis of current voltage characteristics oflow-temperature-processed polysilicon thin-film transistors

The relationship between device performance and trap state density in polysilicon films was investigated. The density in the silicon energy gap was obtained by fitting the calculated on-state current versus gate voltage curve to the measured one for low-temperature (⩽600°C) processed polysilicon TFTs fabricated under various conditions, such as different deposition temperatures and annealing methods for crystallization. On-state current was markedly improved by reducing the density near band edges in the gap, and the improvement was realized by depositing the films at around 500°C in an LPCVD system or employing laser annealing instead of thermal annealing at 600°C. Off-state current was reduced to a great extent by reduction of the density around the midgap by using a plasma-hydrogenation technique     

Performance of thin-film transistors on polysilicon films grown bylow-pressure chemical vapor deposition at various pressures

Defect properties of undoped low-pressure chemical-vapor-deposited (LPCVD) polysilicon films have been investigated by capacitance techniques on a simple metal-oxide-semiconductor (MOS) capacitor structure. The results show that the effective density of bulk and interface trap states is almost independent of the deposition pressure. After reducing the polysilicon film thickness by etching, although the grain size decreases due to the columnar mode of growth at low pressures, the trap states density reduces significantly. This finding could be explained by the hypothesis that, during the growth of the material, impurities are segregated at the film surface by fast diffusion through the grain boundaries. The transport properties of 0.5-μm-thick polysilicon films deposited at a pressure ranging from 100 to 0.5 mtorr were evaluated from measurements on thin-film transistors (TFTs). The results demonstrate that at high pressures the grain boundaries and at low pressures the polysilicon-SiO₂ interface roughness scattering are the main factors in determining the transistor performance     

Reverse short-channel effect in metal-induced laterallycrystallized polysilicon thin-film transistors

A reverse short-channel effect, manifested by an increase in the transistor threshold voltage as the channel length is reduced, is observed in conventional metal-induced laterally crystallized thin-film transistors. Such an effect has not been observed in regular solid phase crystallized thin-film transistors and can be eliminated by a brief hydrogen plasma treatment     

Dynamic hot-carrier induced degradation in n-channel polysilicon thin-film transistors

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.     

Effects of hot carriers in offset gated polysilicon thin-film transistors

The effects of hot carriers on the characteristics of intrinsic offset gated n-channel polysilicon thin-film transistors (TFTs), with channel length L = 10 μm, have been studied in relation to the offset length ΔL. From the evolution of the transfer and output characteristics during stress, the degree of the device degradation is deduced. In devices with ΔL = 0.5 and 1 μm, the on-state current is substantially reduced, whereas the subthreshold region remains almost unaffected. In devices with ΔL = 2 μm, the transfer characteristics are shifted first positively after short stressing time and then negatively, the on-state current is still substantially reduced and well-defined kink is formed in the subthreshold region. The device degradation is found to become more pronounced as the gate offset length increases. A model explaining the post-stress performance of offset gated devices is presented.     

基于表面势的多晶硅晶体管漏电流物理模型

提出了一种基于薄层电荷模型、陷阱态密度和表面势的多晶硅薄膜晶体管漏电流物理模型。模型采用非迭代的运算方法, 简单且适用于所有大于平带电压的工作区域。 考虑了包括高斯分布的深能态和指数分布的带尾态在内的陷阱分布形式, 陷阱分布参数的提取通过光电子调制谱方法实现。通过模型与现有实验结果的比较, 得到一致的符合结果。     

Stability of N-channel polysilicon thin-film transistors with ECRplasma thermal gate oxide

The effects of electrical stress on n-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) plasma gate oxide have been investigated. The plasma-hydrogenerated low-temperature (⩽600°C) TFT's exhibited very a small increase of threshold voltage (ΔV_th<0.3 V) under the stress conditions (V_gs=15 V, V_ds=0 V ~15 V, and stress time=5×10⁴ s). The ΔV_t h was larger for the stress in the linear region than in the saturation region. It was found that the device degradation for the stress in the saturation region was caused by the hot-carriers. Increase of OFF current was maximum for the stress at V_gs=V_ds while for the stress at V_gsds, degradation of transconductance was the dominant effect seen     

Activation energy of source-drain current in hydrogenated andunhydrogenated polysilicon thin-film transistors

The activation energy of the drain current in polysilicon thin-film transistors (TFTs) and the effects of hydrogenation on this energy are discussed. The activation energy data are fitted using different models of the density of states in the material. It is shown that a model which assumes a distribution of brand tail states and localized deep states can account for the activation energy data of unhydrogenated polysilicon TFTs. However, the activation energy data on hydrogenated TFTs cannot be explained with the band tail model. Instead, a simple model of deep states localized at the grain boundary can fit this data quite accurately. Also, it is shown that there is a characteristic kink in the activation energy data of the hydrogenated TFTs which is a signature of the location of the deep states relative to the valence band edge. Analysis indicates that these deep states are located approximately 0.36 eV from the valence band edge. This value is consistent with that obtained from absorption measurements using photothermal deflection spectroscopy     

Polycrystalline silicon thin-film transistors fabricated by defect reduction methods

Fabrication of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) at a low temperature is reported. 13.56 MHz-oxygen plasma at a 100 W, 130 Pa at 250/spl deg/C for 5 min, and heat treatment at 260/spl deg/C with 1.3/spl times/10/sup 6/-Pa-H/sub 2/O vapor for 3 h were applied to reduction of the density of defect states in 25-nm-thick silicon films crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Defect reduction was numerically analyzed. Those treatments resulted in a high carrier mobility of 830 cm/sup 2//Vs and a low threshold voltage of 1.5 V at a laser crystallization energy density of 285 mJ/cm/sup 2/.     

Characteristics of p-channel polysilicon conductivity modulatedthin-film transistors

A p-channel polysilicon conductivity modulated thin-film transistor (CMTFT) is demonstrated and experimentally characterized. The transistor uses the concept of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. The conductivity modulation is achieved by injecting minority carriers (electrons) into the offset region through a diode added to the drain. Experimental results show that the conductivity modulation in the p-channel device is as effective as that in the n-channel device. This structure can provide 1.5 to 2 orders of magnitude higher on-state current than that of the conventional offset drain thin-film transistor (TFT) at drain voltage ranging from -15 V to -5 V while still maintaining low leakage current and simplicity in device operation. The p-channel CMTFT can be combined with the n-channel CMTFT to form CMOS high-voltage drivers, which is very suitable for use in fully integrated large-area electronic applications     

Effects of hydrogenation on the performance and hot-carrierendurance of polysilicon thin-film transistors

Statistical analysis was performed to investigate the performance and reliability of hydrogenated polysilicon thin-film transistors (TFTs) in relation to the hydrogenation process. The hydrogenation was performed in pure H₂ plasma and in plasma of 4% H₂ diluted in Ar or He gas. TFTs hydrogenated in H₂/Ar or H₂/He plasma have lower on-voltage and better uniformity compared to the nonhydrogenated devices due to passivation of grain boundary dangling bonds. Hot-carrier experiments demonstrate that electron trapping is the dominant mechanism at the early stages of the degradation process and generation of interface and grain boundary traps as the stress proceeds further. The overall results indicate that devices hydrogenated in H₂/He plasma are the most reliable in terms of uniformity and hot-carrier stress