Newly structured expandable 52-Mbit/s, 48-channel time-division switching LSI with 2.4 Gbit/s throughput

An expandable Si bipolar 2.4 Gbit/s throughput, 52 Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4 Gbit/s and a power-dissipation of 5.3 W are achieved by adopting a low-voltage swing four-serial-gated differential bipolar circuit design and super self-aligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems of future B-ISDN.<>     

2 Gbit/s, 16*16 expandable high-speed space-division-switch LSI using SST

A Si bipolar 2 Gbit/s 16*16 high-speed space-division-switch LSI is described. High-speed operation of 2 Gbit/s and low-power dissipation of 2.8 W are achieved by adopting a new expandable structure, a very low voltage swing-differential bipolar circuit design and a super self-aligned process technology (SST-1A). This LSI is applicable to future B-ISDN HDTV switching systems.<>     

1 Gbit/s high-speed bit-synchronisation LSI for B-ISDN

The CCITT recommended that the bit rates for synchronous digital hierarchy (SDH) should be multiples of 155.52 Mbit/s. In handling high-speed data (such as 622.08 Mbit/s) in B-ISDN switching systems, there are problems associated with waveform degradation caused by impedance mismatching and amplitude attenuation. A countermeasure is the regeneration of the distorted waveforms using the system clock in each board. A bit-synchronisation circuit allows distorted waveforms to be regenerated and simplifies the design of timing between boards. The author have developed a high-speed bit-synchronisation LSI with excellent jitter tolerance in the 600 Mbit/s region and which has a simple circuit structure. The LSI features a circuit structure based on an elastic store, Si-bipolar super self-aligned process technology (SST),/sup 1/ and careful timing design. It can handle three different bit-rates (622.08, 155.52, and 51.84 Mbit/s) and has a maximum bit rate of 1 Gbit/s.<>     

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

An 80 Gbit/s asynchronous transfer mode (ATM) switch multichip module (MCM) of dimensions 114×160×6.5 mm has been fabricated. This MCM can support high-density mounting and high-speed interconnection among large-scale-integrated (LSI) chips. Using LSI, ceramic-substrate, high-speed/high-power connector, and compact liquid-cooling technologies, an 80 Gbit/s ATM switching module has been built     

Guided-wave optical chip-to-chip interconnections

An optical interconnection technique using a high-silica guided-wave optical circuit composed of channel waveguides and a mixer is proposed for LSI interchip communications. An experimental 4-chip interconnection circuit has 1 Gbit/s transmission capacity performance with an optical power margin of 3 dB.     

Silicon bipolar decision circuit handling bit rates up to 5 Gbit/s

A high-speed silicon bipolar decision circuit is presented which operates up to 5 Gbit/s. It may serve as a subcomponent for integration in a regenerator/repeater circuit for multi-gigabit fiber-optic trunk lines. The circuit was implemented in a standard bipolar silicon technology featuring oxide-wall isolation, 2-μm emitter stripe widths, and a transit frequency of 9 GHZ atV_{CE} = 1V. The measured clock-phase-margin of the decision circuit at 4 Gbit/s corresponds to two thirds of a bit slot and to half a bit slot at 5 Gbit/s. The minimum input sensitivity at 4 Gbit/s is less than 150 mV.     

Fully transparent multiplexing and transport of 10 GbE-LANPHY signals for 44.6 Gbit/s-based RZ-DQPSK WDM transmission

Transparent 10 GbE-LANPHY transport for 44.6 Gbit/s RZ-DQPSK WDM transmission is demonstrated for the first time. A single-chip 43/44 Gbit/s OTN framer LSI that supports fully transparent STM-64/10 GbE multiplexing and DQPSK precoding is adopted.     

Diode multiplexer in the multi-Gbit/s range

A clocked multiplexer circuit was realised which provided 4.48 Gbit/s, 5 Gbit/s, and 7.84 Gbit/s output-pulse streams for p.c.m.-type input tributaries at 1.12 Gbit/s, 0.25 Gbit/s, and 1.12 Gbit/s, respectively. The circuit employed essentially ultra-broadband 180° hybrids, step-recovery diodes, and GaAs Schottky-barrier diodes. Output voltages up to 2 V were obtained across a load of 50 ?. The pulse width of the output pulses was approximately 100 ps.     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

IP网中40 Gbit/s链路需求解决方案

本文阐述了IP网中40 Gbit/s链路需求的背景,介绍了40 Gbit/s关键技术,提出了IP网中40 Gbit/s链路应用解决方案.     

1 Gbit/s, 32*32 high-speed space-division switching module for broadband ISDN using SST LSIs

A high-speed 32*32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8*8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.<>     

High performance 10-12.5 Gbit/s modulator driver in InP SHBT technology

A high performance modulator driver circuit is presented using 4" InP SHBT technology. The IC was developed for driving EAM modulators in OC-192 (10 Gbit/s) and with forward error correction (FEC: 10.7 Gbit/s or 12.5 Gbit/s) optical fibre systems. The monolithic integrated circuit features output amplitude control, output crossing point control and output DC offset control. Measured results show the circuit operates at 10 to 12.5 Gbit/s with a swing of 3.1 V/sub p-p/ at each output and 20/18 ps rise/fall times. The power dissipation is 1.4 W with a standard power supply of -5.2 V.     

56 Gbit/s analogue PLL for clock recovery

A clock-recovery circuit is reported that employs a phase-locked loop (PLL) at 56.88 Gbit/s, and is demonstrated by locking to a 28.44 GHz sinusoidal signal while two additional circuits with adapted on-chip passive components are locked to 29 and 39 Gbit/s pseudorandom bit sequences. To the knowledge of the authors, this is the first demonstration of an integrated PLL integrated circuit for clock recovery at a data rate well above 40 Gbit/s     

4 Gbit/s pseudo-noise generator using GaAs MESFETs

A multiplexing gate using GaAs MESFETs is described and operation up to 4 Gbit/s is demonstrated. A 2 Gbit/s pseudo-noise generator which can deliver NRZ or RZ signals has been implemented with this circuit; the corresponding output sequences are shown.     

Fully monolithic integrated 43 Gbit/s clock and data recoverycircuit in InP HEMT technology

A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 μm gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 2³¹-1 PRBS data signal at 43 Gbit/s     

160 Gbit/s full optical time-division demultiplexing using FWM ofSOA-array integrated on PLC

160 Gbit/s full time-division demultiplexing using a semiconductor optical amplifier hybrid integrated demultiplexer on a planar lightwave circuit is demonstrated. Error-free, demultiplexing from a 160 Gbit/s signal to eight-channel, 20 Gbit/s signals is successfully demonstrated     

A Line Termination Circuit for Burst-Mode Digital Subscriber Loop Transmission

This paper describes a line termination circuit for burst-mode bidirectional digital subscriber loop transmission. It incorporates the most advanced LSI technology to obtain compactness, low cost, and high reliability. Two CMOS LSI's have been developed; one is a line termination LSI (LT) and another is a circuit termination LSI (CT). LT LSI adopts a novelRCactive filter-type equalizer and decision feedback bridged tap equalizer suitable for incorporation in LSI and provides high performance. By using these LSI's, a line termination circuit realizes a reach of over 5 km at 88 kbit/s bidirectional digital transmission. This paper describes each LSI and shows total performance characteristics in detail.     

10‐Gbit/s Wireless Communication System at 300 GHz

A 10‐Gbit/s wireless communication system operating at a carrier frequency of 300 GHz is presented. The modulation scheme is amplitude shift keying in incoherent mode with a high intermediate frequency (IF) of 30 GHz and a bandwidth of 20 GHz for transmitting a 10‐Gbit/s baseband (BB) data signal. A single sideband transmission is implemented using a waveguide‐tapered 270‐GHz highpass filter with a lower sideband rejection of around 60 dB. This paper presents an all‐electronic design of a terahertz communication system, including the major modules of the BB and IF band as well as the RF modules. The wireless link shows that, aided by a clock and data recovery circuit, it can receive 2⁷?1 pseudorandom binary sequence data without error at up to 10 Gbit/s for over 1.2 m using collimating lenses, where the transmitted power is 10 μW.     

40 Gbit/s fully monolithic clock recovery IC usingInAlAs/InGaAs/InP HEMTs

The authors describe a 40 Gbit/s fully monolithic clock recovery integrated circuit (IC) fabricated using 0.1 μm InAlAs/InGaAs/InP HEMTs. The IC utilises injection locking, and consists of a half bit delay, an exclusive OR gate and a T-type flip-flop. The IC extracts a half-rate clock signal from a 39.81312 Gbit/s 2³¹-1 pseudo-random bit sequence signal without any other external components     

A time division multiplexer IC for bit rates up to about 2 Gbits/s

A bipolar 4:1 time-division multiplexer IC developed for a planned 1.12 Gbit/s optical communication system is presented. Without resorting to sophisticated technology, the high speed was achieved by modification of well-known circuit concepts and by careful circuit optimization. With a current-switch output, reliable operation was measured to over 2 Gbit/s compared to over 1.5 Gbit/s if emitter-follower outputs are used. The experimental results agree very well with the simulation predictions.