边界扫描板级链路测试性设计方法研究

边界扫描技术是一种新型的VLSI电路测试及可测性设计方法.但是在扫描链路的设计中如何将不同厂家、不同型号、不同工作电压的BS器件实现JTAG互连,如何将边界扫描测试、在线编程和在线仿真结合起来一直是一个亟待解决的问题.为解决上述问题,本文提出了两种基于边界扫描技术的板级动态链路设计方法.这种可测性设计技术不仅能完成边界扫描测试,还能完成在线编程或在线仿真等功能,具有很好的测试设计灵活性.     

嵌入式数据库SQLite在边界扫描测试系统中的应用

为提高边界扫描测试效率,设计并开发了一种基于嵌入式开源数据库SQLite的边界扫描测试系统.简单陈述了嵌入式数据库SQLite技术、边界扫描测试原理,阐述了边界扫描测试软件模块功能设计和测试数据处理实现方法.测试结果表明,嵌入式数据库SQLite解决了边界扫描测试系统中存在的数据管理问题,提高了数据存储和读取效率,节省了处理数据所占用的资源,降低系统成本,具有较好的应用前景.     

基于边界扫描的板级动态扫描链路设计策略

边界扫描技术是一种新型的VLSI电路测试及可测性设计方法。但是在扫描链路的设计中如何将不同厂家、不同型号、不同工作电压的Bs器件实现JTAG互连，如何将边界扫描测试、在线编程和在线仿真结合起来一直是一个亟待解决的问题。为了解决上述问题，文中提出了两种基于边界扫描技术的板级动态链路设计方法。该方法不仅能完成边界扫描测试，还能完成在线编程或在线仿真等功能，具有很好的测试设计灵活性。     

VXI边界扫描模块接口电路的设计

根据IEEE1149.X标准和VXI总线规范,采用EDA技术对VXI边界扫描模块的接口电路进行了研究和设计,通过仿真和实际测试验证了设计的正确性,很好地将VXI总线技术和边界扫描技术融合在一起,成功研制了一种符合IEEE1149.X标准的C尺寸VXI边界扫描模块。在VXI总线测试领域拓展了边界扫描测试功能,不增加测试系统的成本和复杂性,解决了VXI总线应用领域集成电路的测试问题。     

边界扫描测试技术的原理及其应用

边界扫描技术是一种应用于数字集成电路器件的标准化可测试性设计方法，他提供了对电路板上元件的功能、互连及相互间影响进行测试的一种新方案，极大地方便了系统电路的测试。自从1990年2月JTAG与TEEE标准化委员会合作提出了“标准测试访问通道与边界扫描结构”的IEEE1149．1—1990标准以后，边界扫描技术得到了迅速发展和应用。利用这种技术，不仅能测试集成电路芯片输入／输出管脚的状态，而且能够测试芯片内部工作情况以及直至引线级的断路和短路故障。对芯片管脚的测试可以提供100％的故障覆盖率，且能实现高精度的故障定位。同时，大大减少了产品的测试时间，缩短了产品的设计和开发周期。边界扫描技术克服了传统针床测试技术的缺点，而且测试费用也相对较低。这在可靠性要求高、排除故障要求时间短的场合非常适用。特别是在武器装备的系统内置测试和维护测试中具有很好的应用前景。本文介绍了边界扫描技术的含义、原理、结构，讨论了边界扫描技术的具体应用。     

基于NIOS边界扫描测试平台的开发

阐述一种新颖的基于NIOS边界扫描测试平台的设计,提出了采用SOPC技术的一种更加灵活、高效的嵌入式系统新解决方案.该方案将边界扫描主控器系统的多功能模块集成在Altera公司推出的低成本、高密度、具有嵌入式NIOS软核CPU的现场可编程门阵列(FPGA)上,大大提高了系统设计的灵活性、边界扫描的测试效率.同时USB接口技术的应用使得边界扫描测试系统具有热插拔,传输速率快等优点.详细论述了具有自主知识产权的JTAG总线控制模块的设计和NIOS平台上USB固件开发.实验结果表明,此测试平台的设计正确有效,能够进行精确的故障诊断.     

基于边界扫描技术的集成电路测试系统设计与实现

介绍了边界扫描的技术原理,及其在集成电路测试中的具体应用,并给出了一种基于边界扫描技术的板级集成电路测试系统的方案及实现。     

基于边界扫描技术的板级测试分析

随着支持IEEE1149.1标准的边界扫描芯片的广泛应用,传统的电路板测试方法如使用万用表、示波器"探针",已不能满足板级测试的需求,相反一种基于板级测试的边界扫描技术得到了迅速发展。对边界扫描测试技术的原理进行了剖析,根据边界扫描测试系统的使用规则对板级测试方法进行了分析、提出了整体测试流程,最后在通用测试的基础上进行了二次开发,提出了提高电路板测试覆盖率的方法。     

边界扫描技术在含DSP电路板测试与诊断的研究与应用

针对含DSP电路板的测试与诊断问题,本文提出一种利用边界扫描技术和传统的外部输入矢量测试相结合的方法,对含DSP电路板中的边界扫描器件的器件及非边界扫描器件进行了测试.测试结果表明:该测试方法对边界扫描器件及非边界扫描器件可进行有效的故障检测和故障隔离,并可将故障隔离至最小的测试单元.同时详细阐述了测试诊断方案、硬件设...     

基于边界扫描技术和Tcl语言的DualSRAM测试设计

集成电路（IC）的迅猛发展促进了测试技术的研究和发展,支持IEEE1149.1标准的边界扫描芯片的广泛应用,使得边界扫描测试技术日益被重视。Tcl语言是一种简明、高效、移植性强的语言,它与边界扫描技术的结合,扩展了芯片测试技术的应用,使得IC的测试更加灵活。本文以DualSRAM的测试设计为例,介绍了以边界扫描技术为基础的Tcl语言的应用,同时根据测试开发中遇到的问题,提出了一些可测性设计（DFT）的建议。     

Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits

This paper will propose an overall portfolio of different modern test techniques, like reduced pin-count test, SoC multi-site test, low channel cost ATE, test vector compression, bandwidth matching, and advanced probing technologies, to lower the cost of test. The overall economic benefits, the potential synergies, the overall tradeoffs, and the scalability of the benefits of these techniques, are complex to understand and currently not well understood. This problem will be analyzed in this paper by using technical cost modeling. The dependency of the benefits on different applications will be analyzed by modeling the test cost for four different applications. It will be shown that the right match between the application and a combination of the described techniques can result in a significant reduction of the cost of test. Moreover, it will be shown that this optimal match evolves during technology progress and can enable a scalable reduction of the cost of test.     

大规模集成电路中开闭路测试的优化与改进

现有的直流开闭路测试无论在测试时间还是测试效率上已经遇到了很大的瓶颈,其测试时间将近1s,导致整体的测试时间很长,极大地影响了产能。文章介绍的动态开闭路测试以及VTT终端开闭路测试在测试流程以及测试方法上做了很大的优化和改进,从而很好地解决了测试时间上的瓶颈问题。通过对相同被测芯片测试数据的比较后发现,这一改进对大规模生产的半导体工厂来说是一个显著降本增效的方法,对于一个批次的芯片,节约的时间可以达到40min。除此之外,这种动态测试方法还可以普及到其他静态直流测试项中,由此在测试时以及测试效率上所得到的优化是显而易见的。     

Scan Test Strategy for Asynchronous-Synchronous Interfaces

In the coming years, the well-known synchronous design style will not be able to keep pace with the increase speed and capabilities of integration of advanced processes. New design paradigms, like core reuse of the already designed synchronous modules and asynchronous designs, are considered in order to cope with the ever increasing complexity. The future SoCs will contain multiple synchronous and asynchronous cores. Asynchronous design will become more and more common among digital designers, while synchronous-asynchronous interactions will emerge as a key issue in the future SoC designs.This paper will present test strategies for 2-phase asynchronous-synchronous interfaces and vice versa. It will be shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors will be able to test all stuck-at-faults within the asynchronous-synchronous interfaces.     

合理安排电磁兼容测试在产品测试中的顺序

实例表明,将电磁兼容试验置于气候环境影响试验与机械要求试验之前与之后进行所得的结果存在较大的差异。通过分析认为气候环境影响试验与机械要求试验可能会影响被测设备中的某些材料特性,从而影响设备的电磁兼容性能。因此电磁兼容测试应与其他测试一起形成一个有机的整体,合理安排测试顺序,可以更好地发现产品的质量问题,提高产品的技术优势和市场竞争力。     

Research on the Efficiency Improvement of Design for Testability Using Test Point Allocation

Traditional design for testability (DFT) is arduous and time-consuming because of the iterative process of testability assessment and design modification. To improve the DFT efficiency, a DFT process based on test point allocation is proposed. In this process, the set of optimal test points will be automatically allocated according to the signal reachability under the constraints of testability criteria. Thus, the iterative DFT process will be completed by computer and the test engineers will be released to concentrate on the system design rather than the repetitive modification process. To perform test point allocation, the dependency matrix of signal to potential test point (SP-matrix) is defined based on multi-signal flow graph. Then, genetic algorithm (GA) is adopted to search for the optimal test point allocation solution based on the SP-matrix. At last, experiment is carried out to evaluate the effectiveness of the algorithm.     

Measurement and the networked future

The increasingly interconnected world is setting new demands on test and measurement suppliers. The authors outline how the industry is rising to the challenge. Instrument manufacturers must always be at the leading edge of the technologies they are involved in, why they play a critical role in establishing new communication standards and protocols. Just about any device that is subject to test and measurement is likely to be connected to some form of network. Testing these networked elements presents a whole new set of problems for the test and measurement engineer, especially for those individuals unfamiliar with modern communications technology. Looking ahead, most test and measurement instruments will be connected to a network. This represents a natural progression for design engineers, both in the way they use instruments and in the way they access data acquired or analysed by an instrument. In future, an engineer will no longer have to move from an office to a lab environment just to check the execution of a test suite-the check will be performed over a network. Similarly, access to an instrument won't be restricted to a single engineer in one location-the whole engineering team will concurrently view the instrument set-up and acquired data, regardless of the physical location of the individual team members or system under test     

多线程测试序列在USB/UCB半自动检测与维护系统中的应用

在USB/UCB半自动检测与维护系统中采用多线程进行测试提高效率,并通过调用测试序列,使用户可以对测试项目进行随意组合(选择要测试的项目和测试顺序),并且采用队列的方式使数据采集和数据处理两个线程之间保持了同步,使保存的测试结果更加准确,并准确地反映了整个测试过程(项目测试的顺序)。     

浅谈氧化锌避雷器带电测试

由于氧化性避雷器在长期运行中都会经受热、冲击破坏和阀片老化而导致故障,所以必须对其进行定期的预防性试验,而相邻的电气主设备往往不能及时停运,因而必须采用带电测试的方法对氧化锌避雷器加以测试。在测试中,因为是带电进行,由于方法不当或外界电磁干扰等因素往往对试验结果产生很大的影响,采用合理的试验方法,消除外界各种因素的干扰显得尤为重要。     

传声器管的高温反偏试验

近年来,驻极体传声器发展很快,对于传声器管的电参数要求更高,尤其高温反偏试验更为严苛。多年来,对此项试验发现与以前有关资料中的结果存在某些差异,给予补充说明。     

Centralized large-scale clinical testing in a commercial environment

This article will deal with the role of the large medical testing laboratory, and its increasing importance to the medical community. It will illustrate the necessary interrelationship of technological advances in instrumentation, transportation, and communication. The role of the computer with supporting electronic and electrical systems in handling a large volume of clinical test data will be outlined. From a scientific and economic standpoint, it will demonstrate the merits of volume testing in the areas of quality control, speed, and cost per test. Good business practices and the importance of continuing research, continuing education, continuing growth as adjuncts of the large clinical testing laboratory will be noted. It will show the ability of the large medical testing laboratory, with private capitalization, vision and sound management to keep pace with the demands of physicians for test data for patient diagnosis, evaluation and treatment, today and in the future.