A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.     

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.     

Active-feedback frequency-compensation technique for low-power multistage amplifiers

An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

Amplifier techniques for combining low noise, precision, and high-speed performance

A monolithic operational amplifier is presented which optimizes voltage noise both in the audio frequency band, and in the low frequency instrumentation range. In addition, the design demonstrates that the requirements for low noise do not necessitate compromising the specifications in other respects. Techniques are set forth for combining low noise with high-speed and precision performance for the first time in a monolithic amplifier. Achieved results are: 3 nV//spl radic/Hz white noise, 80 nV/SUB p-p/ noise from 0.1 to 10 Hz, 17 V//spl mu/s slew rate, 63 MHz gain-bandwidth product, 10 /spl mu/V offset voltage, 0.2 /spl mu/V//spl deg/C drift with temperature, 0.2 /spl mu/V/month drift with time, and a voltage gain of two million.     

Transconductance with capacitances feedback compensation for multistage amplifiers

A new performance-boosting frequency compensation technique is presented, named Transconductance with Capacitances Feedback Compensation (TCFC). A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. An optimized TCFC amplifier has been implemented, and fabricated in a 0.35-/spl mu/m CMOS process. The TCFC amplifier driving a 150-pF load capacitor achieved 2.9-MHz gain-bandwidth product dissipating only 45-/spl mu/W power with a 1.5 V supply, which shows a significant improvement in MHz/spl middot/pF/mA performance.     

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.     

A high precision monolithic super-beta operational amplifier

A single-chip (67/spl times/90 mil) integrated-circuit operational amplifier using thin-film resistors and super-gain transistors has been designed to achieve dc follower accuracies of 0.001 percent with 100-k/spl Omega/ source resistance. The circuit achieves gains of 140 dB using thermally balanced layout designs for both input and output stages, nulled drifts of 0.3 /spl mu/V//spl deg/C, and offset currents well under 1 nA. All other dc specifications including power-supply variation error (PSRR), common-mode gain error (CMRR), etc., are in the 1-10 ppm error range; and a procedure is given by which long-term drifts of less than 10 /spl mu/V/month can be assured. AC performance is comparable to general-purpose integrated-circuit operational amplifiers, i.e., f/SUB t/=300 kHz and slew rate of 1.2 V//spl mu/s at gain of ten. The circuit is externally compensated for unity gain with a single 390-pF capacitor and is fully input and output protected.     

Self-biased cross-coupled low-cost fully-differential CMOS operational amplifier

A low-cost fully-differential operational amplifier (opamp) using a novel self-biased cascode output stage and cross-coupled input stage is proposed. Fabricated in only an 84/spl times/67 /spl mu/m/sup 2/ area with TSMC 0.35 /spl mu/m technology, and loaded with more than 100 pF capacitance, the opamp possesses 60 dB DC gain, 3 V//spl mu/s slew rate, 7.8 MHz unity-gain bandwidth, and -48 dB total harmonic distortion.     

A complete high-speed voltage output 16-bit monolithic DAC

A new single-chip 16-bit monolithic digital/analog converter (DAC) with on-chip voltage reference and operational amplifiers has achieved /spl plusmn/0.0015% linearity, 10 ppm//spl deg/C gain drift, and 4-/spl mu/s settling time. Novel elements of the 16-bit DAC include: the fast settling open-loop reference with a buried Zener, a fast-settling output operational amplifier without the use of feedforward compensation, and a modified R-2R ladder network. Thermal considerations played a significant role in the design. The DAC is fabricated using a 20-V process to reduce device sizes and therefore die size. All laser trimming including temperature drift compensation is performed at the wafer level. The converter does not require external components for operation.     

A low-voltage micropower JFET/bipolar operational amplifier

A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W).     

High-speed driving scheme and compact high-speed low-power rail-to-rail class-B buffer amplifier for LCD applications

A high-speed driving scheme and a compact high-speed low-power rail-to-rail class-B buffer amplifier, which are suitable for small- and large-size liquid crystal display applications, are proposed. The driving scheme incorporates two output driving stages in which the output of the first output driving stage is connected to the inverting input and that of the second driving stage is connected to the capacitive load. A compensation resistor is connected between the two output stages for stability. The second output stage is used to improve the slew rate and the settling time. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. A rail-to-rail folded-cascode differential amplifier is used to amplify the input signal difference and supply the bias voltages for the second stage. An experimental prototype output buffer implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the circuit draws only 7-/spl mu/A static current and exhibits the settling times of 2.7 /spl mu/s for rising and 2.9 /spl mu/s for falling edges for a voltage swing of 3.3 V under a 600-pF capacitance load with a power supply of 3.3 V. The active area of this buffer is only 46.5/spl times/57/spl mu/m/sup 2/.     

Micropower high-performance SC building block for integrated low-level signal processing

A switched-capacitor instrumentation amplifier which uses correlated-double sampling to reduce the amplifier offset is discussed. Additional offset caused by clock-related charge injection is cancelled by a symmetrical differential circuit topology and a three-phase clocking scheme. An experimental low-power test cell has been integrated, showing 100 /spl mu/V equivalent offset voltage and input noise equal to 270 /spl mu/V. For a fixed gain equal to 10- and 9-kHz sampling frequency, the power dissipation is 36 /spl mu/W (power supply: 5 V); the circuit measures only 0.2 mm/SUP 2/.     

220-GHz metamorphic HEMT amplifier MMICs for high-resolution imaging applications

In this paper, the development of 220-GHz low-noise amplifier (LNA) MMICs for use in high-resolution active and passive millimeter-wave imaging systems is presented. The amplifier circuits have been realized using a well-proven 0.1-/spl mu/m gate length and an advanced 0.05-/spl mu/m gate length InAlAs/InGaAs based depletion-type metamorphic high electron mobility transistor technology. Furthermore, coplanar circuit topology in combination with cascode transistors was applied, leading to a compact chip size and an excellent gain performance at high millimeter-wave frequencies. A realized single-stage 0.05-/spl mu/m cascode LNA exhibited a small-signal gain of 10 dB at 222 GHz, while a 0.1-/spl mu/m four-stage amplifier circuit achieved a linear gain of 20 dB at the frequency of operation and more than 10 dB over the bandwidth from 180 to 225 GHz.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

A high-performance all-enhancement NMOS operational amplifier

An NMOS operational amplifier has been designed and fabricated using only enhancement mode MOSFETs in a circuit that employs a novel feedforward compensation scheme. Specifications achieved include high open loop gain (2200), low-power (15 mW or less depending on the load), fast settling time (0.1 percent settling time in 3 /spl mu/s for a 4 V input step and a 10 pF load), and small area. While this amplifier uses only a small number of transistors, its performance is comparable to that of recent depletion load amplifiers. Fewer critical steps are needed to fabricate this amplifier, making it attractive for large analog/digital LSI circuits.     

A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.     

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

A mixed-signal BiCMOS front-end signal processor for high-temperature applications

A mixed-signal ASIC that implements an ultrasound front-end receiver in a 0.6 /spl mu/m BiCMOS HotASIC technology that features metal/metal capacitors and poly1/poly2 resistors is described. The ASIC includes a low-noise amplifier (LNA), a programmable gain amplifier (PGA), an output differential amplifier (ODA), and a second-order sigma-delta modulator (SDM), and is the most compact system for high-temperature ultrasound applications reported in literature. The circuit has a programmable gain and is designed for measuring the signal response (200 kHz to 700 kHz) from an ultrasound transducer. At 48 MHz clock frequency and 200/spl deg/C, the power consumption is 85 mW from a single 5 V supply. The die area of the chip is 5.52 mm/sup 2/.