基于提高效率方法的CMOS功率放大器设计

利用共源共栅电感可以提高共源共栅结构功率放大器的效率。这里描述了一种采用共源共栅电感提高效率的5.25GHz WLAN的功率放大器的设计方法,使用CMOS工艺设计了两级全差分放大电路,在此基础上设计输入输出匹配网络,然后使用ADS软件进行整体仿真,结果表明在1.8V电源电压下,电路改进后于改进前相比较,用来表示功率放大器效率的功率附加效率（PAE）提高了两个百分比。最后给出了功放版图。     

自适应偏置SOI CMOS功率放大器的设计

基于IBM 0.18 μm SOI CMOS工艺,设计了一款用于WLAN的高效率CMOS功率放大器。为了提高电路的可靠性,该放大器的驱动级和输出级均采用自适应偏置电路,使得共栅管和共源管的漏源电压分布更为均衡。该芯片采用两级共源共栅结构,片内集成了输入匹配电路和级间匹配电路。测试结果表明,该放大器的增益为23.9 dB,1 dB压缩点为23.9 dBm,效率为39.4%。当测试信号为IEEE 802.11g 54 Mb/s,在EVM为3%处,输出功率达到16.3 dBm。     

一种自偏置低压共源共栅带隙基准电路设计

随着CMOS工艺的发展,器件尺寸逐渐缩小,短沟道效应的影响日益突出。共源共栅电流源可以很好地抑制小尺寸效应,但其消耗的电压余度较大,偏置电路设计繁琐。因此介绍了一种采用自偏置低压共源共栅电流源的带隙基准电路结构,用两个电阻代替了偏置电路。仿真结果显示,该带隙基准电路的最低电源电压约为2.98V,相对于普通的共源共栅结构,降低了2个MOSFET阈值电压;工作在最低电源电压下,功耗约为270μW,相对于带偏置电路的结构,降低约75μW。仿真结果证明,该电路能够简化共源共栅电路的设计和调试,并减少低压共源共栅电路的功耗。     

改进型折叠式共源共栅运算放大器电路的设计

在套筒式共源共栅、折叠式共源共栅运放中,折叠式共源共栅运算放大器凭借较大的输出摆幅和偏置电压的较低等优点而得到广泛运用。但是,折叠式的这些优势是以牺牲较大的功耗、较低的电流利用率而换取的。本文以提高电流利用率为着手点设计了一种改进的折叠式共源共栅运算放大器,在相同的电压和负载下改进的折叠式共源共栅运算放大器能显著提升跨导、压摆率和噪声性能。仿真结果表明在相同功耗和面积的条件下,改进的折叠式共源共栅运算放大器的单位增益带宽和压摆率是折叠式共源共栅运放的3倍。     

高性能折叠式共源共栅运算放大器的设计

折叠式共源共栅结构能够提供足够高的增益,并且能够增大带宽、提高共模抑制比和电源电压抑制比.基于Chartered 0.35 μm工艺,设计了一种折叠式共源共栅结构的差分输入运算放大器,给出了整个电路结构.Spectre仿真结果表明,该电路在3.3V电源电压下直流开环增益为121.5dB、单位增益带宽为12 MHz、相位裕度为61.4°、共模抑制比为130.1dB、电源电压抑制比为105 dB,达到了预期的设计目标.     

一款高性能共源共栅运算放大器设计

基于CSMC 0.5μm标准CMOS工艺,采用复用型折叠式共源共栅结构,设计一种折叠式共源共栅运算放大器。该电路在5V电源电压下驱动5pF负载电容,采用Cadence公司的模拟仿真工具Spectre对电路进行仿真。结果表明,电路开环增益达到了71.7dB,单位增益带宽为52.79MHz,开环相位裕度为60.45°。     

一款用于77/79 GHz汽车雷达的宽带功率放大器

采用55 nm CMOS工艺设计并实现了一款用于77/79 GHz汽车雷达的宽带功率放大器。设计了一个大尺寸的W波段功率单元,优化功率单元内部结构及外部无源器件连接方法,减少了功率单元的寄生电容、电感和电阻。采用一种将晶体管寄生电容考虑在内的变压器耦合谐振峰值控制技术,提高了功放的增益及带宽。在共源共栅结构基础上,采用了一种共栅短路技术,提升输出功率并改善功放稳定性。测试结果表明,该功率放大器具有良好的输入、输出匹配性能,3 dB带宽达到9 GHz,饱和输出功率达到15.5 dBm,峰值效率达到12.5%,实现了优异的FOM值。     

一种用于5G通信的高稳定双模功率放大器

采用国产40 nm CMOS工艺,设计了一种用于5G通信的28 GHz双模功率放大器。功率级采用大尺寸晶体管,获得了高饱和输出功率。采用无中心抽头变压器,消除了大尺寸晶体管带来的共模振荡问题。在共源共栅结构的共栅管栅端加入大电阻,提高了共源共栅结构的高频稳定性。采用共栅短接技术,解决了大电阻引起的差模增益恶化问题。在级间匹配网络中采用变容管调节,实现了双模式工作,分别获得了高功率增益和高带宽。电路后仿真结果表明,在高增益模式下,该双模功率放大器获得了20.8 dBm的饱和输出功率、24.5%的功率附加效率和28.1 dB的功率增益。在高带宽模式下,获得了20.6 dBm的饱和输出功率、22.6%的功率附加效率和12.2 GHz的3 dB带宽。     

一种高CMRR和PSRR的共源共栅放大器

针对传统运算放大器共模抑制比和电源抑制比低的问题,设计了一种差分输入结构的折叠式共源共栅放大器。本设计采用两级结构,第一级为差分结构的折叠式共源共栅放大器,并采用MOS管作为电阻,进一步提高增益、共模抑制比和电源电压抑制比;第二级采用以NMOS为负载的共源放大器结构,提高增益和输出摆幅。基于LITE—ON40V1．0μm工艺,采用Spectre对电路进行仿真。仿真结果表明,电路交流增益为125．8dB,相位裕度为62.8°,共模抑制比140．9dB,电源电压抑制比125．5dB。     

基于0.13μm CMOS的WiFi功率放大器设计

基于TSMC 0.13 μm CMOS工艺,设计了一款适用于无线保真(WiFi)收发机的发射端、工作在2.4 GHz且增益可控的三级级联功率放大器.驱动级采用单管结构,后两级采用共源共栅(MOSFET)结构.利用调节共源共栅晶体管栅极的电容来改变栅极电压的相位,进而弥补了共源共栅结构的劣势,增加了整个系统的线性度和增益.另外,使用外部数字信号控制每级偏置的大小来适应不同的输出需求.整个结构采用电源电压:第一级为1.8V,后两级为3.3V,芯片面积为1.93 mm×1.4 mm.利用Candence Spectre RF软件工具对所设计的功率放大器进行仿真.结果表明,在2.4 GHz的工作频点,功率放大器的饱和输出功率为24.9 dBm,最大功率附加效率为22％,小信号增益达到28 dB.     

Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

包络跟踪的J类功率放大器设计

为了提高功率放大器的回退效率以更好地适应第五代移动通信系统的高峰均比信号的需求,文中提出了一种基于包络跟踪的J类功率放大器的设计方法,通过对电源调制器的设计来动态调制J类功率放大器的供电电压,以降低漏极直流功耗,实现提高功率放大器效率的目标.最终的测试结果表明在3.4～3.6GHz频率范围内,当采用带宽20MHz、峰均...     

High‐Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

This paper proposes a high‐efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current‐mode transformer‐based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18‐μm RF‐CMOS process with a supply voltage of 3.3 V. The measured gain, P_1dB, and efficiency at P_1dB are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25‐dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.     

改进负载调制的GaN Doherty功率放大器及其线性化

在分析传统Doherty负载调制的基础上,通过选取合适的峰值放大器负载阻抗和采用较高的偏置电压,增强了Doherty功率放大器的负载调制,使其适用于大范围（9dB）回退情况下的应用。为了验证分析的有效性,设计和实现了一个具有100MHz瞬时带宽的2.55GHz GaN Doherty功率放大器。测试结果表明：在工作带宽内饱和功率约为49.4dBm,平均峰值效率为64%,9dB回退时的平均效率约为40%。当使用5载波100MHz带宽LTE-advanced信号激励时,在平均输出功率为40.2dBm时效率可达40.3%,经过数字预失真校正过的邻道泄漏比（ACLR）低于-48dBc,达到较好的线性度。     

高效率Class F功率放大器的设计

本文基于InGaP/GaAs HBT(HBT为异质结双极晶体管)工艺设计了一款高效率的Class F功率放大器。文中首先描述了F类功率放大器的特点和电路原理,然后对放大器的设计过程如匹配电路设计技术、谐波抑制对功率效率的影响,以及偏置电路的设计等问题做了详细的讨论。测试结果表明,设计的功率放大器在电源电压为5V,输出功率为37dBm时,效率达68%。     

A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

A two-stage differential linear power amplifier(PA) fabricated by 0.18μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power,efficiency and harmonic performance.Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency(PAE) is 35.4%,the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled.The total area with ESD protected PAD is 1.2×0.55 mm~2.Sy...     

A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOS Envelope-Tracking OFDM Power Amplifier

A monolithic SiGe BiCMOS envelope-tracking power amplifier (PA) is demonstrated for 802.11g OFDM applications at 2.4 GHz. The 4-mm² die includes a high-efficiency high-precision envelope amplifier and a two-stage SiGe HBT PA for RF amplification. Off-chip digital predistortion is employed to improve EVM performance. The two-stage amplifier exhibits 12-dB gain, <5% EVM, 20-dBm OFDM output power, and an overall efficiency (including the envelope amplifier) of 28%.     

A CMOS RF Polar Transmitter of a UHF Mobile RFID Reader for High Power Efficiency

A CMOS radio frequency (RF) polar transmitter architecture for a UHF (860–960 MHz) RF identification (RFID) reader is proposed, which consists of a switch-mode CMOS power amplifier (PA) and an analog pulse-shaping filter implemented in 0.25-$mu$ m CMOS process. The amplitude modulation of a amplitude shift keying signal is performed by simply switching the common gate transistor of a cascode power amplifier. Extremely low power consumption is achieved when the PA is switched off. The power efficiency of the transmitter is enhanced not only by using switching power amplifier but also by employing this architecture.      

A 0.25-/spl mu/m 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer

A 2.4-GHz CMOS power amplifier (PA) with an output power 20 dBm using 0.25-/spl mu/m 1P5M standard CMOS process is presented. The PA uses an integrated diode connected NMOS transistor as a diode linearizer. It is believed that this is the first reported use of the diode linearization technique in CMOS PA design. It shows effective improvement in linearity from gain compression and ACPR measured results. Measurements are performed by using an FR-4 PCB test fixture. The fabricated power amplifier exhibits an output power of 20 dBm and a power-added efficiency as high as 28%. The obtained PA performances demonstrate the standard CMOS process potential for medium power RF amplification at 2.4 GHz wireless communication band.