Monolithic Power-Combining Techniques for Watt-Level Linear Power Amplifiers in 0.18 CMOS*

设计了三个输出功率为瓦级的线性CMOS功率放大器(PA),该PA主要应用于高速移动通讯。为了实现瓦级输出功率,两个工作频率为2.4 GHz 的PA采用片上并联合成变压器将多个功放级的输出电流信号相加,另一个工作频率为1.95 GHz的PA采用片上串联合成器将多个功放级的输出电压信号相加。同时在PA的设计过程中采用了如下线性度提高技术：有源偏置、二极管线性电路、多栅晶体管并联和谐波短路等。以上三款PA均采用TSMC 0.18 射频CMOS工艺进行设计并流片。根据测量结果,两个2.4 GHz PA的功率增益分别为33.2 dB、34.3 dB,最高输出功率分别为30.7 dBm、29.4 dBm,最高功率附加效率(PAE)分别为29%、31.3%。根据仿真结果,1.95GHz PA的功率增益、最高输出功率和最高PAE分别为：37.5dB、34.3 dBm和36.3%。     

3G CMOS功率放大器提升移动设备可靠性和数据传输率

Black Sand是业内第一家做3G CMOS射频功率放大器(PA)的公司,前不久,该公司推出了两条新的3G CMOS射频功率放大器(PA)产品线(BST34和BST35系列),它们可显著提升各种手机、平板电脑和数据卡的可靠性和数据传输量并降低成本。该产品系列包括6     

HARRIS Z10发射机功放原理及维护

HARRIS Z10CD全固态调频发射机整机由16块功放模块组成,每个功放模块包含两个独立的射频功率放大器(PA),每个射频功率放大器可以输出功率425 W。功放模块是可热插拔器件,能在发射机工作状态时拔下或插上。每块功放模块通常能在环境温度     

基于GaN 的3. 4~ 3. 6 GHz 高增益Doherty 功率放大器

基于两级功率放大器架构,设计了一款平均输出功率为37 dBm(5 W)的高增益Doherty 功率放大器。 该器件通过增加前级驱动功率放大器提高Doherty 功率放大器的增益,采用反向Doherty 功率放大器架构,将λ/4 波 长传输线放置在辅助功放后端,相位补偿线放置在主功放前端,并使主功放输出匹配网络采用双阻抗匹配技术实现 阻抗变换,如此可扩宽功率放大器的工作带宽。连续波测试结果显示:3. 4~3. 6 GHz 工作频段内,饱和输出功率在 44. 5 dBm 以上,功率饱和工作点PAE 在43. 9%以上;在平均输出功率(37 dBm,5 W)工作点,回退量大于7. 5 dB,功 率附加效率PAE 为36. 8%以上,功率增益在31 dB 以上。     

增强版FPGA综合方案解决原型设计难题

Silicon Laboratories公司针对GSM/GPRS市场推出据称业界首款采用CMOS工艺技术,体积最小、且具有高性能和高功率的单芯片功率放大器(PA)-Si4300.     

基于AD8302的PA非线性补偿方案

正射频功率放大器是发射机系统中非线性最强的器件,特别是为了提高功率效率,射频功放基本工作在非线性状态,因此线性化功率放大器设计技术己成为线性化发射机系统的关键技术。由于调制方式的改变,导致射频发射端PA(Power-Amplifier)要求更高的线性度。由此,引入了DPD(Digital Pre-Distortion)技术来提高PA的AM-AM、AM-PM的线性度。在采用一般的DPD技术时,通常     

基于中和电容的60 GHz CMOS功率放大器设计

功率放大器（Power Amplifier, PA）是射频前端重要的模块,本文基于SMIC 55 nm RF CMOS 工艺,设计了一款60 GHz 两级差分功率放大器。针对毫米波频段下,硅基CMOS晶体管栅漏电容（Cgd）严重影响放大器的增益和稳定性的问题,采用交叉耦合电容中和技术抵消Cgd影响。通过优化级间匹配网络和有源器件参数,提高了功率放大器的输出功率,增益和效率。后仿结果显示,在1.2V的供电电压下,工作在60 GHz的功率放大器饱和输出功率为11.3 dBm,功率增益为16.2 dB,功率附加效率为17.0%,功耗为62 mW。芯片面积380×570 um2 。     

Axiom Microdevices的CMOS功放为手机制造商提供了优秀的射频方案

Axiom Microdevices目前展示了该公司屡获殊荣的互补金属氧化物半导体功率放大器（CMOS PA）技术。通过开拓性的集成电路技术创新，Axiom Microdevices利用其专利技术为手机制造商提供了一种替代传统砷化镓功率放大器的解决方案，高度集成化的CMOS PA单芯片技术避免了复杂而昂贵的多芯片模块技术，从而确保客户可从CMOS的各项优势中获得诸多好处，包括集成度提高、供应的连续性、可扩展性、功耗和成本的降低。     

提高共源共栅CMOS功率放大器效率的方法

利用共源共栅电感可以提高共源共栅结构功率放大器的效率。这里描述了一种采用共源共栅电感提高效率的5.25 GHz WLAN的功率放大器的设计方法,使用CMOS工艺设计了两级全差分放大电路,在此基础上设计输入输出匹配网络,然后使用ADS软件进行整体仿真,结果表明在1.8 V电源电压下,电路改进后与改进前相比较,用来表示功率放大器效率的功率附加效率(PAE)提高了两个百分比。最后给出了功放版图。     

高线性度CMOS射频AB类功率放大器设计

CMOS射频AB类功率放大器广泛应用于单片集成无线芯片内.采用恒定最大电流的方法对其效率进行分析,采用归一化输入电压的方法对其线性度进行分析.利用AB类功率放大器系统增益的非线性与CMOS跨导非线性相互补偿,提高了CMOS射频AB类放大器的线性度.基于TSMC 0.18μm CMOS混合信号工艺,设计了一款两级射频AB类功率放大器.该射频功率放大器差动输入,单端输出,工作频段为804~940MHz,工作电压为3V.仿真指标为:增益为11dB,输出1dB压缩点为17.2dBm,OIP3为18.2dBm,附加效率为37%.     

26 GHz高回退效率Doherty功率放大器

针对功率回退时主路功率放大器不能有效进入饱和状态导致Doherty功率放大器回退效率低的问题,通过降低主路功率放大器的供电电压,实现了高回退效率,同时增大辅路功放管的尺寸弥补了电路的总输出功率。基于0. 1μm GaAs pHMET工艺,设计了一个26 GHz两级非对称的Doherty功率放大器。仿真结果表明,在26 GHz时增益达到16 dB,功放的饱和输出功率为27. 4 dBm,峰值功率附加效率(PAE)为40. 7%,输出功率回退7 dB时PAE仍达到38%,与传统Doherty功率放大器相比具有更高的回退效率,版图的尺寸为3. 2 mm×2. 2 mm。     

250 W HVHBT Doherty With 57% WCDMA Efficiency Linearized to ${-}$55 dBc for 2c11 6.5 dB PAR

A two-way symmetrical Doherty amplifier exhibiting 250 W saturated power has been developed using high-voltage HBT (HVHBT) GaAs technology biased at 28 V on the collector. Greater than 57% collector efficiency at 50 W (47 dBm) average output power has been demonstrated while achieving -55 dBc linearized ACPR at 5 MHz offset using a two-carrier-side-by-side WCDMA input signal with 6.5 dB PAR measured at 0.01% probability on the CCDF. In addition, a two-stage HVHBT lineup exhibiting 450 W (56.5 dBm) peak power has been demonstrated. The output stage consists of a pair of 250 W two-way symmetrical Doherty amplifiers power combined using a low-loss branchline combiner and driven by a single-ended 100 W class AB high-efficiency amplifier. The lineup demonstrated 44% PAE at 100 W (50 dBm) average output power with 25 dB lineup gain while achieving - 55 dBc linearized ACPR at 5 MHz offset using a two-carrier-side-by-side WCDMA input signal with 6.5 dB PAR measured at 0.01% probability on the CCDF. The lineup exhibits 400 W (56 dBm) PldB at 60% PAE CW, with 45% PAE at 6 dB backoff.     

A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each other's phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39% PAE (using 1.85-V supply). The active die area is 1.2 mm/sup 2/.     

A Handset Power Amplifier With High Efficiency at a Low Level Using Load-Modulation Technique

A new monolithic-microwave integrated-circuit power amplifier for cellular handsets has been implemented using the load-modulation concept of the Doherty amplifier, which has a high efficiency at a low power level. In order to get a compact module, the$lambda/4$transmission line for the load modulation is replaced by a passive high-pass$pi$-network, and the load-modulation circuit is also modified to function as a power-matching circuit of the main amplifier. The amplifier has two modes of operation, low- and high-power modes, controlled by a control voltage. At the high power mode, both the main and auxiliary amplifiers are operational and, at the low power mode, only the main amplifier generates output power enhancing the efficiency. For the code-division multiple-access environment, the amplifier at the low-power mode provides power-added efficiency (PAE) of 39.8% and an adjacent channel power ratio (ACPR) less than 49.8 dBc at 23.1 dBm, and the high-power mode PAE of 37.9% and ACPR of 46.4 dBc at 28 dBm. The efficiency is improved by approximately 18.8% at$ P_ out=23$dBm by the load-modulation technique. For the advanced mobile phone system-mode operation, the amplifier delivers 26.1 dBm with PAE of 53% and 30.8 dBm with 48.7% at the low and high modes, respectively.     

A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier

This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm². Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P₁ dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P₁ dB is above 10% and the PAE degradation is less than 29%.     

A High-Efficient CMOS RF Power Amplifier With Automatic Adaptive Bias Control

A 2.4-GHz Doherty power amplifier (PA) is developed in 0.18-mum CMOS technology. An automatic adaptive bias control circuit is integrated with the auxiliary PA to improve the overall performance of the PA. Operated at 3V, the P_{1 dB} and associated power-added-efficiency (PAE) of the PA are 21dBm and 33%, respectively. At the output power 6-dB backoff from P_{1 dB}, the PAE remains 21%. The limited PAE degradation at backoff power levels makes the PA suitable for the applications with high peak-to-average power ratio     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

A high-efficiency CMOS +22-dBm linear power amplifier

Modern wireless communication systems require power amplifiers with high efficiency and high linearity. CMOS is the technology of choice for complete systems on a chip due to its lower costs and high integration levels. However, it has always been difficult to integrate high-efficiency power amplifiers in CMOS. In this paper, we present a new class of operation (parallel A&B) for power amplifiers that improves both their dynamic range and power efficiency. A prototype design of the new amplifier was fabricated in a 0.18-/spl mu/m CMOS technology. Measurement results show a PAE that is over 44% and the measured output power is +22 dBm. In comparison to a normal class A amplifier, this new design increases the 1-dB compression point (P1dB) by over 3 dB and reduces dc power consumption by over 50% within the linear operating range.