A Symmetric Complementary Structure for RF CMOS Analog Squarer and Four-Quadrant Analog Multiplier

A symmetric complementary structure for CMOS analog squarer and four-quadrant multiplier is proposed and analyzed. Analog squarer and a four-quadrant analog multiplier by utilizing the square-algebraic identity in the MOS triode region are presented. The squarer has a symmetric complementary configuration of the push-pull source follower and provides high performance in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The squarer, with –3 dB bandwidth of 1.3 GHz, had a nonlinearity error less than 1% over input signal range of ±1 V. The multiplier is basically constructed by voltage subtractors (for differential function of inputs) and sum-squaring as well as difference-squaring core circuits (for multiplication of two differential inputs signals). The multiplier has a nonlinearity error less than 1% over ±0.5 V input range. The circuit provides a –3 dB bandwidth higher than 1.3 GHz and exhibits a THD lower than 1% with a 1 V peak-to-peak input voltage, which dissipating 2.6 mW. The second-order effects including mismatch effects are discussed. The proposed circuits will be useful in various RF analog signal-processing applications.     

An Analog Squaring Technique Based on Asynchronous Sigma–Delta Modulation

Accurate analog squarers are required for different signal processing functions, such as amplitude modulation, frequency shifting, signal power estimation, and neural and image processing. Transistor-level analog squarers suffer from limited accuracy, particularly in modern deep-submicrometer technology, where the squared law of the MOS transistor in the saturation region is no longer valid. Based on the asynchronous sigma–delta modulator (ASDM), a new circuit that provides the squared value of the input signal is proposed. For slowly varying input signals, the filtered output is a replica of the squared input signal. In this brief, the proposed analog squarer is studied, and the analytical results are validated by simulation in the time domain. The effect of analog imperfections on the accuracy of the squarer is also analyzed by showing that a high signal-to-noise-plus-distortion ratio can be obtained for typical values of the mismatch and up to frequencies near half the maximum frequency of the ASDM limit cycle.      

多功能AB类四象限模拟乘法器

在AB类电流镜基础上应用跨导线性原理设计出一种新颖的电流平方/电流跟随器,并以该模块为基本单元综合设计出一种多功能的四象限模拟乘法器.该乘法器在内部结构和元件参数不变的情况下,根据输入、输出信号的选择可以实现电压模式和电流模式乘法器.采用TSMC 0.35μm CMOS集成工艺对电路进行PSPICE仿真测试,结果表明提...     

New CMOS four-quadrant multiplier and squarer circuits

A CMOS four-quadrant multiplier and a squarer using the positive feedback loops consisting of the current mirrors are presented. Simulation results are given to verify the theoretical analysis. The input range of this multiplier is over ±2.5V with the linearity error less than 1% and its-3dB bandwidth is about 20MHz. The total harmonic distortion is less than 1% with the input range up to ±2V. The squarer has a ±1.6V input range. Second order effects such as mobility reduction and transistor mismatch have been discussed. Experimental results by using discrete components are also given. The proposed circuits are expected to be useful in analog signal-processing applications.     

Analogue squarer and multiplier based on floating-gate MOStransistors

A simple squarer based on floating-gate MOS transistors is presented. The squarer has rail-to-rail input range with less than 0.5% non-linearity error. Using this squarer single-ended and/or differential signals can be processed without additional circuitry. Also, a four quadrant analogue multiplier can be realised using the proposed squarer. Simulation results are given to verify the theoretical analysis     

Chopper Stabilization of Analog Multipliers, Variable Gain Amplifiers, and Mixers

We describe a general offset-canceling architecture for analog multiplication using chopper stabilization. Chopping is used to modulate the offset away from the output signal where it can be easily filtered out, providing continuous offset reduction which is insensitive to drift. Both square wave chopping and chopping with orthogonal spreading codes are tested and shown to reduce the offset down to the microvolt level. In addition, we apply the nested chopping technique to an analog multiplier which employs two levels of chopping to reduce the offset even further. We discuss the limits on the performance of the various chopping methods in detail, and present a detailed analysis of the residual offset due to charge injection spikes. An illustrative CMOS prototype in a 0.18 mum process is presented which achieves a worst-case offset of 1.5 muV. This is the lowest measured offset reported in the DC analog multiplier literature by a margin of two orders of magnitude. The prototype multiplier is also tested with AC inputs as a squarer, variable gain amplifier, and direct-conversion mixer, demonstrating that chopper stabilization is effective for both DC and AC multiplication. The AC measurements show that chopping removes not only offset, but also 1/f noise and second-order harmonic distortion.     

一种低压高线性CMOS模拟乘法器设计

提出了一种新颖的CMOS四象限模拟乘法器电路．该乘法器基于交叉耦合平方电路结构,并采用减法电路来实现。它采用0．18μmCMOS工艺,使用HSPICE软件仿真。仿真结果显示,该乘法器电路在1．8V的电源电压下工作时,静态功耗可低至80μW,其线性输入范围达到±0．3V,-3dB带宽可达到1GHz,而且与先前低电压乘法器电路相比,在同样的功耗和电源电压下,具有更好的线性度。     

Parallel squarer design using pre-calculated sums of partial products

The partial product matrix of a parallel squarer is symmetric. To reduce the depth of the partial product matrix, it can be typically folded, shifted and merged. A high performance parallel squarer design technique using pre-calculated sums of some partial products is presented. It is shown that the proposed method reduces the area, propagation delay and power consumption compared with previous squarers.     

Low-voltage reduced complexity cells for MOS translinear loops

A novel bias scheme for realizing low-voltage second-order translinear loops is introduced in this paper. The provided design examples include current geometric-mean, squarer/divider, and multiplier/divider cells. The performed comparison shows that the derived analog signal processing blocks offer reduced circuit complexity and improved performance, compared with the corresponding already published counterparts.     

Analogue BiCMOS squarer and its applications

A BiCMOS squarer using active attenuators which has been fabricated in a 10 μm BiCMOS process is presented. Experimental results show that the nonlinearity of the squarer can be kept below 2%, across the entire input voltage range of ±0.3 V. Its -3 dB bandwidth is measured to be ~1 MHz. Moreover, based on the proposed squarer circuits, a four-quadrant multiplier and a vector summation circuit have also been realised. The proposed circuits are expected to be useful in analogue signal processing applications     

Sampled-data and continuous-time squarers in MOS technology

Two MOS squarer circuits are presented. One implementation operates on sampled-data signals, while the second uses continuous-time operation. Both squarers achieve the square-law function with MOS transistors operating in the nonsaturation region biased with zero drain-to-source voltage. Benefits of nonsaturated operation are discussed. The sampled-data squarer is practically independent of component mismatches and clock pulse-width mismatches     

Low power FGMOS-based four-quadrant current multiplier circuits

In this paper, low-power, high-speed four-quadrant analog multiplier circuits have been presented, based on simple current squarer circuits. The squarer circuits consist of a floating-gate MOS transistor, operating in saturation region plus a resistor. These multipliers have a unique property of greatly reduced power as they do not have any bias currents. For performance evaluation, the designs are simulated using HSPICE software in 0.18 µm (level-49 parameters) TSMC CMOS technology. Using ± 0.5 V DC supply voltages for the first design, the simulation resulted in a maximum linearity error of 0.8%, the ? 3 dB bandwidth of 635 MHz, the Total Harmonic Distortion of 0.57% (at 1 MHz), and maximum and static power consumption of 40.4 and 5.75 µW, respectively. Corresponding values for the second design with 1 V DC supply voltage are 0.4%, 394.8 MHz, 0.72%, 44 and 11.4 µW, respectively. Furthermore, in order to verify the robustness and reliability of the proposed works, Monte Carlo analysis are performed. For the mentioned analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are considered.     

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.     

An improved universal CMOS current-mode analogue function synthesiser

A CMOS integratable current-mode analogue function synthesiser circuit is presented. The proposed circuit is based on approximating the required function using its sixth-order Taylor series expansion. These approximations can be implemented by adding the weighted output currents of a number of basic building blocks, built around a basic current squarer, and a constant current. The proposed circuit can simultaneously realise 32 different mathematical functions and can be easily expanded to accommodate many others. SPICE and Monte Carlo simulation results demonstrating the circuit performance are included.     

Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers

A novel technique for operating MOS Translinear loops at very low supply voltages is described, based on the use of Flipped Voltage Followers for biasing the loops. The resulting topologies, suited to standard CMOS processes, can be successfully applied to a varied repertory of low-voltage analog circuits, such as squarers, multipliers, filters, oscillators, and RMS-DC converters. Measurement results for a geometric-mean and a squarer/divider circuit demonstrate on silicon the usefulness of this technique.     

Low-voltage bulk-driven class AB four quadrant CMOS current multiplier

In this paper a low voltage bulk-driven class AB four quadrant current multiplier is proposed. For the proposed multiplier a bulk-driven class AB current mode cell has been developed and the drain current equations for NMOS and PMOS transistors of the proposed cell have been derived. This cell is used as a basic building block for bulk-driven low voltage current squarer and copier circuit, which is finally used as the fundamental building block of the proposed low-voltage bulk-driven current multiplier operating at ±1 V. All the circuits are simulated using SPICE for 0.25 μm CMOS technology.     

A High-Frequency Field-Programmable Analog Array (FPAA) Part 1: Design

The design of a high-frequency field-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.     

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.     

Demonstration of an Analog IC Function Maintenance Strategy, Including Direct Calibration, Built-in Self-test, and Commutation of Redundant Functional Blocks

A new analog subsystem maintenance strategy is presented that can be used to improve the accuracy, reliability, yield, and testability of analog and mixed-signal ICs. This scheme is a generally applicable design approach that combines hybrid redundancy, direct subcircuit parameter adjustment (calibration), and on-chip analog function verification (built-in self-test). Improvements are realized in a system-transparent fashion through careful function block commutation. The cost is a moderate die area increase. This design strategy is applicable to a wide range of moderately complex analog functions. An example analog function is used here to illustrate this new maintenance approach. Experimental data demonstrate the capabilities of this new approach to analog IC design fortestability.     

Design and application of precise analog computational circuits

New versatile building blocks for implementing analog functional circuits such as a multiplier, a squarer, and a square rooter based on functional terms of a differential input circuit are proposed and implemented in 0.25 um CMOS process. The input range of these circuits is over  ±1.0 V with a high linearity of less than 4% for 3.3 V power supply. The  ?3 dB bandwidth of all discussed circuits has been measured to over 200 MHz. The functional circuit size is 340 μm², and its typical power consumption is about 90 uW.